I want to build a T-flip flop in Verilog. So far I have written the following code, but I wish they could see if it is correct please. The machine I was using to make the code is in the image.
module flopJK(q,j,k,c);
input j,k,c;
output q;
reg q;
always #(posedge c)
begin
case ({j,k})
{1'b0,1'b0}:begin q=q; end
{1'b0,1'b1}:begin q=1'b0; end
{1'b1, 1'b0}:begin q=1'b1; end
{1'b1, 1'b1}:begin q=~q; end
endcase
end
endmodule
T-flip flop in Verilog:
There are several scope of improvements I think.
reset signal is not there, which is required to initialise your FF.
Always use non-blocking assignment for sequential logic and blocking for combinational logic.
Here is your code.
module flopJK (q,j,k,c, r);
input j,k,c, r;
output q;
reg q;
always #(posedge c, negedge r)
begin
if (r != 1)
q <= 1'b0;
else
begin
case ({j,k})
{1'b0,1'b0}:begin q <= q; end
{1'b0,1'b1}:begin q <= 1'b0; end
{1'b1, 1'b0}:begin q <= 1'b1; end
{1'b1, 1'b1}:begin q <= ~q; end
endcase
end
end
endmodule
Related
I am looking to create an AND gate which gets the result after a delay of lets say 10ns an my clock is 500 ps. How will i delay the assignment without using # delays ?
I have tried to make a counter which increments but how to model it so that it only starts when my input changes. Also the input won't change till the first output is evaluated and assigned. Initial Counter is 0 and lets say delay is 3'b111 so i want the counter to go from 1 to 3'b111 and then assign it to y. Inputs are a and b to the and gate.
always#(posedge clk)begin
if (!reset) begin y <=0; counter <=0; end
else begin
counter <= counter +1'b1;
if(counter==delay)begin
y <= a & b;
counter <=0;
end
end
Well if your clock cycle is 500 ps then you will need to count to a higher value to reach 10ns. I rewrote your code and also added a testbench for you to try. It's kind of sloppy, I usually write vhdl and not verilog. Hope this helps.
//Module
module count_and (
input clk,
input reset,
input a,
input b,
output reg y,
output reg [4:0] counter
);
reg ready;
always#(posedge clk)begin
if (!reset) begin
y <=0;
counter <=0;
ready <= 0;
end
else if (ready == 1'b1) begin
counter <= counter +1'b1;
if (counter==5'b10011) begin
y <= a & b;
counter <=0;
ready <= 0; //turn it off after passing to y
end
end
end
always #(a,b) begin
ready <= 1'b1;
end
endmodule
//TestBench
`timescale 1ps/1ps
module tb_count ();
reg a,b;
reg clk;
reg reset;
wire [4:0] counter;
wire y;
initial begin
clk = 1'b1;
reset = 1'b0;
a = 1'b0;
b = 1'b0;
end
always begin
reset <= #50 1'b1;
clk = #250 ~clk;
a <= #1000 1'b1;
b <= #1000 1'b1;
end
count_and count_and_inst (
.clk(clk),
.reset(reset),
.a(a),
.b(b),
.y(y),
.counter(counter)
);
endmodule
I'm doing a synthesis of a digital block and I need a D-Flip-Flop with 2 asynchronous resets.
(The reason is that I will drive one reset with an available clock, and I will use the second one to reset all the registers of my digital block)
I prepared the following code:
module dff_2rst(q,qn,clk,d, rst,clear);
input clk,d, rst, clear ;
output q,qn;
reg q,qn;
always #(posedge clk or posedge rst or posedge clear) //asynchronous reset
begin
(* full_case, parallel_case *)
case({rst, clear})
2'b00: begin
q <= d;
qn<=~d;
end
default: begin
q <= 1'b0;
qn <=1'b1;
end
endcase
end
endmodule
But I get the following error:
The statements in this 'always' block are outside the scope of the synthesis policy. Only an 'if' statement is allowed at the top level in this always block. (ELAB-302)
*** Presto compilation terminated with 1 errors. ***
I also tried with
if(~rst & ~clear)
but I have errors too.
Do you have an idea to correct my code? Thanks a lot!
The standard way to write a async reset, set (clear) flip-flop in Verilog RTL is:
always #(posedge clk or posedge rst or posedge clear) begin
if (rst) begin
// Aysnc Reset
q <= 'b0 ;
end
else if (clear) begin
// Async Clear
q <= 'b0 ;
end
else begin
// Sync logic here
q <= d;
end
end
assign qn = ~n;
The little trick for qn requires it qn be a wire, currently defined as a reg. reg q,qn; should just be reg q;
Also for cleaner code a new header type is cleaner and avoids repetition:
module dff_2rst(
input clk,
input d,
input rst,
input clear,
output reg q,
output qn );
Thank you Morgan. Your code was inspiring to me. I couldn't use
assign qn=~q;
Because I got the error:
qn is not a valid left-hand side of a continuous assignment.
But I modified your code in the following manner and it works:
module dff_2rst(q,qn,clk,d, rst,clear);
input clk,d, rst, clear ;
output q,qn;
reg q,qn;
always #(posedge clk or posedge rst or posedge clear) //asynchronous reset
//
begin
if (rst) begin
// Aysnc Reset
q <= 'b0 ;
qn<= 'b1 ;
end
else if (clear) begin
// Async Clear
q <= 'b0 ;
qn<= 'b1 ;
end
else begin
// Sync logic here
q <= d;
qn<= ~d;
end
end
endmodule
I'm trying to implement simple JK Flipflop in Verilog (Modelsim). But I'm getting the following error
The generate if condition must be a constant expression.
Here is the code which I'm using
module jkfflop(J,K,clk,Q);
input J,K,clk;
output Q;
if(J==0 & K==1)
begin
assign Q = 0;
end
else if(J==1 & K==0)
begin
assign Q = 1;
end
else if(J==1 & K==1)
begin
assign Q = ~Q;
end
endmodule
Can someone help me
In Verilog RTL there is a formula or patten used to imply a flip-flop. for a Positive edge triggered flip-flop it is always #(posedge clock) for negative edge triggered flip-flops it would be always #(negedge clock).
An Example of positive edge triggered block.
reg [7:0] a;
always #(posedge clock) begin
a <= b;
end
Normally you want a reset as well, a Synchronous reset would be:
reg [7:0] a;
always #(posedge clock) begin
if ( reset == 1'b1 ) begin
a <= 'b0;
end
else begin
a <= b;
end
end
It is more common is ASIC design to require an active low Asynchronous :
reg [7:0] a;
always #(posedge clock, negedge reset_n) begin
if ( reset_n == 1'b0 ) begin
a <= 'b0;
end
else begin
a <= b;
end
end
Note that the asynchronous reset has reset in the sensitivity list this makes the block respond to changes in the signal.
The way you have used (reused) assign is incorrect.
Using the above info your module would become:
module jkfflop(
input J,
input K,
input clk,
output Q );
always #(posedge clk) begin
if(J==1'b0 && K==1'b1) begin
Q <= 'b0;
end
else if(J==1'b1 && K==1'b0) begin
Q <= 1'b1;
end
else if(J==1'b1 & K==1'b1) begin
Q <= ~Q;
end
end
endmodule
But could be written with a case statement:
always #(posedge clk) begin
case({J,K})
2'b0_0 : Q <= Q ;
2'b0_1 : Q <= 1'b0;
2'b1_0 : Q <= 1'b1;
2'b1_1 : Q <= ~Q ;
endcase
end
I'm trying to get a triangle waveform, but my code doesn't work! I think the "if conditions" are organised wrong but I can't find the mistake My wave goes up like it should be and it falls down by 90° after achieving the top
module pila(clk,res,out2);
input clk,res;
output [0:7]out2;
reg [0:7]out2;
always #(posedge clk)
begin
if (res)
begin
if(out2<=8'b11111111)
out2=out2+1;
else if(out2>=8'b00000000)
out2=out2-1;
else out2=8'b00000000;
end
else out2=8'b00000000;
end
endmodule
module testbench;
reg clk,res;
wire [0:7]out2;
pila Sevo(clk,res,out2);
always #2 clk=~clk;
initial
begin
clk=0;res=0;
#2 res=1;
end
initial #5000 $finish;
endmodule
You need some signal to indicate which direction you are currently counting. Also use the non-blocking assignment operator <= rather than the blocking assignment operator =.
module pila(clk,res,out2);
input clk,res;
output [0:7]out2;
reg [0:7]out2 = 8'h00;
reg count_down = 1'b0;
always #(posedge clk)
begin
if (count_down == 1'b0)
begin
if (out2==8'b11111111) // check for top of count
begin
count_down <= 1'b1;
out2<=out2-1;
end
else
out2<=out2+1;
end
else
begin
if(out2==8'b00000000) // check for bottom of count
begin
count_down <= 1'b0;
out2<=out2+1;
end
else
out2<=out2-1;
end
end
endmodule
The if(out2<=8'b11111111) condition is always evaluating to true. This is because out2 range is 0 to 255. Try adding another flop to control the direction, for example downup where 1 means decrement and 0 means increment.
if (out2 == 8'h00) begin
downup <= 1'b0; // up
out2 <= 8'h01;
end
else if (out2 == 8'hFF) begin
downup <= 1'b1; // down
out2 <= 8'hFE;
end
else if (downup) begin // down
out2 <= out2 - 1;
end
else begin // up
out2 <= out2 + 1;
end
Other issues:
Use non-blocking assignment (<=) for synchronous logic.
Typically reset (and set) conditions are declared before synchronous logic assignment
Little-Endian ([7:0]) is more commonly used for packed arrays (previously known as vectors) then Big-Endian ([0:7]), http://en.wikipedia.org/wiki/Endianness
Working example: http://www.edaplayground.com/x/4_b
I wrote a behavioral program for booth multiplier(radix 2) using state machine concept. I am getting the the results properly during the program simulation using modelsim, but when I port it to fpga (spartan 3) the results are not as expected.
Where have I gone wrong?
module booth_using_statemachine(Mul_A,Mul_B,Mul_Result,clk,reset);
input Mul_A,Mul_B,clk,reset;
output Mul_Result;
wire [7:0] Mul_A,Mul_B;
reg [7:0] Mul_Result;
reg [15:0] R_B;
reg [7:0] R_A;
reg prev;
reg [1:0] state;
reg [3:0] count;
parameter start=1 ,add=2 ,shift=3;
always #(state)
begin
case(state)
start:
begin
R_A <= Mul_A;
R_B <= {8'b00000000,Mul_B};
prev <= 1'b0;
count <= 3'b000;
Mul_Result <= R_B[7:0];
end
add:
begin
case({R_B[0],prev})
2'b00:
begin
prev <= 1'b0;
end
2'b01:
begin
R_B[15:8] <= R_B[15:8] + R_A;
prev <= 1'b0;
end
2'b10:
begin
R_B[15:8] <= R_B[15:8] - R_A;
prev <= 1'b1;
end
2'b11:
begin
prev <=1'b1;
end
endcase
end
shift:
begin
R_B <= {R_B[15],R_B[15:1]};
count <= count + 1;
end
endcase
end
always #(posedge clk or posedge reset)
begin
if(reset==1)
state <= start;
else
begin
case(state)
start:
state <= add;
add:
state <= shift;
shift:
begin
if(count>7)
state <= start;
else
state <=add;
end
endcase
end
end
endmodule
You have an incomplete sensitivity list in your combinational always block. Change:
always #(state)
to:
always #*
This may be synthesizing latches.
Use blocking assignments in your combinational always block. Change <= to =.
Good synthesis and linting tools should warn you about these constructs.
Follow the following checklist if something does work in the simulation but not in reality:
Did you have initialized every register? (yes)
Do you use 2 registers for one working variable that you transfer after each clock (no)
(use for state 2 signals/wires, for example state and state_next and transfer after each clock state_next to state)
A Example for the second point is here, you need the next stage logic, the current state logic and the output logic.
For more informations about how to proper code a FSM for an FPGA see here (go to HDL Coding Techniques -> Basic HDL Coding Techniques)
You've got various problems here.
Your sensitivity list for the first always block is incomplete. You're only looking at state, but there's numerous other signals which need to be in there. If your tools support it, use always #*, which automatically generates the sensitivity list. Change this and your code will start to simulate like it's running on the FPGA.
This is hiding the other problems with the code because it's causing signals to update at the wrong time. You've managed to get your code to work in the simulator, but it's based on a lie. The lie is that R_A, R_B, prev, count & Mul_Result are only dependent on changes in state, but there's more signals which are inputs to that logic.
You've fallen into the trap that the Verilog keyword reg creates registers. It doesn't. I know it's silly, but that's the way it is. What reg means is that it's a variable that can be assigned to from a procedural block. wires can't be assigned to inside a procedural block.
A register is created when you assign something within a clocked procedural block (see footnote), like your state variable. R_A, R_B, prev and count all appear to be holding values across cycles, so need to be registers. I'd change the code like this:
First I'd create a set of next_* variables. These will contain the value we want in each register next clock.
reg [15:0] next_R_B;
reg [7:0] next_R_A;
reg next_prev;
reg [3:0] next_count;
Then I'd change the clocked process to use these:
always #(posedge clk or posedge reset) begin
if(reset==1) begin
state <= start;
R_A <= '0;
R_B <= '0;
prev <= '0;
count <= '0;
end else begin
R_A <= next_R_A;
R_B <= next_R_B;
prev <= next_prev;
count <= next_count;
case (state)
.....
Then finally change the first process to assign to the next_* variables:
always #* begin
next_R_A <= R_A;
next_R_B <= R_B;
next_prev <= prev;
next_count <= count;
case(state)
start: begin
next_R_A <= Mul_A;
next_R_B <= {8'b00000000,Mul_B};
next_prev <= 1'b0;
next_count <= 3'b000;
Mul_Result <= R_B[7:0];
end
add: begin
case({R_B[0],prev})
2'b00: begin
next_prev <= 1'b0;
end
.....
Note:
All registers now have a reset
The next_ value for any register defaults to it's previous value.
next_ values are never read, except for the clocked process
non-next_ values are never written, except in the clocked process.
I also suspect you want Mul_Result to be a wire and have it assign Mul_Result = R_B[7:0]; rather than it being another register that's only updated in the start state, but I'm not sure what you're going for there.
A register is normally a reg, but a reg doesn't have to be a register.