I have a loop checking the status of a sensor. If it's in one state, I light a LED using digitalWrite (1,HIGH), otherwise, I write LOW. This happens in a tight loop many times a second.
Is it fine to write so many times, or is it better practice to set a flag and only write if the flag has changed?
It shouldn't be a problem for the board. You could also add a short delay at the end of the loop (delay(5);)
Related
I have some tasks in verilog file. And I want to see them in simvision when they are triggered.
Is there any way to find task's triggered point in simvision?
Is this can not be able to visualize in simvision? I know that manner like using print or display statements. But I need to visualize to simvision. Does anyone know that way?
UPDATE
Use a breakpoint
If you don't have access to the source of the task, or cannot modify it, >you could set a breakpoint when the task is called, execute some TCL >commands, then continue the simulation. The TCL commands could toggle a >signal or increment a counter. This could be automated with a small TCL >script. Depending on your situation, this could cause a performance hit on >the simulation time.
I want to know more this manner, would you let me know this way how to make it? Please let me know even if simple I am OK.
I don't think there is a native way to do this, but you should check the documentation that Cadence provides. That said, there are a few options you could employ to get information into the waveform.
Add a counter
If you can modify the source for the task, you can add a global counter somewhere which increments each time the task is called. Then add the counter register to the waveform.
Toggle a bit
Similarly, you could use a single bit and toggle it when the task is called. Using a counter has the advantage that if the task can be called twice in the same time step, you will see the counter increment by 2, whereas the single bit would toggle twice and not be visible in the waveform, unless you have zero-time event capturing enabled.
Use a breakpoint
If you don't have access to the source of the task, or cannot modify it, you could set a breakpoint when the task is called, execute some TCL commands, then continue the simulation. The TCL commands could toggle a signal or increment a counter. This could be automated with a small TCL script. Depending on your situation, this could cause a performance hit on the simulation time.
I am surprised that Linux kernel has infinite loop in 'do_select' function implementation. Is it normal practice?
Also I am interested in how file changes monitoring implemented in Linux kernel? Is it infinite loop again?
select.c source code
This is not an infinite loop; that term is reserved for loops with no exit condition at all. This loop has its exit condition in the middle: http://lxr.linux.no/#linux+v3.9/fs/select.c#L482 This is a very common idiom in C. It's called "loop and a half" and there's a simple pseudocode example here: https://stackoverflow.com/a/10767975/388520 which clearly illustrates why you would want to do this. (That question talks about Java but that's not important; this is a general structured-programming idiom.)
I'm not a kernel expert, but this particular loop appears to have been written this way because the logic of the inner loop needs to run both before and after the call to poll_schedule_timeout at the very bottom of the outer loop. That code is checking whether there are any events to return; if there are already events to return when select is invoked, it's supposed to return immediately; if there aren't any initially, there will be when poll_schedule_timeout returns. So in normal operation the outer loop should cycle either 0.5 or 1.5 times. (There may be edge-case circumstances where the outer loop cycles more times than that.) I might have chosen to pull the inner loop out to its own function, but that might involve passing pointers to too many local variables around.
This is also not a spin loop, by which I mean, the CPU is not wasting electricity checking for events over and over again until one happens. If there are no events to report when control reaches the call to poll_schedule_timeout, that function (by, ultimately, calling __schedule) will cause the calling thread to block -- the CPU is taken away from that thread and assigned to another process that can do something useful with it. (If there are no processes that need the CPU, it'll be put into a low-power "halt" until the next interrupt fires.) When one of the events happens, or the timeout, the thread that called select will get "woken up" and poll_schedule_timeout will return.
On a larger note, operating system kernels often do things that would be considered strange, poor style, or even flat-out wrong, in the service of other engineering goals (efficiency, code reuse, avoidance of race conditions that can only occur on some CPUs, ...) They are written by people who know exactly what they are doing and exactly how far they can get away with bending the rules. You can learn a lot from reading though OS code, but you probably shouldn't try to imitate it until you have a bit more experience. You wouldn't try to pastiche the style of James Joyce as your first exercise in creative writing, ne? Same deal.
Simply put, I want to manipulate two motors in parallel, then when both are ready, continue with a 3rd thread.
Below is image of what I have now. In two top threads, it sets motors B and C to "unlimited", then waits until both trigger the switches, then sets a separate boolean variable for both.
Then in 3rd thread, I poll these two variables with 1 second interval, until AND operation gives true to the loop termination condition.
This is embedded system and all, so it may be ok here, but in "PC programming", this kind of polling loop would be rather horrible thing to do.
Question: Can I do either of both of
wait for variable without this kind of polling loop?
wait for a thread to finish without using a variable at all?
Your question is a bit vague on what you actually want to achieve and using which language. As I understood you want to be able to implement a similar multithreaded motor control mechanism in Labview?
If so, then the answer to both of your questions is yes, you can implement the wait without an explicitly defined variable (other than the error cluster, which you probably would be passing around anyway). The easiest method is to pass an error cluster to both your loops and then use Merge errors to combine the generated errors once the loops are finished. Merge errors will wait until both inputs have data, merges the errors, and passes the merged error cluster on. By wiring the merged error cluster to your teardown function you effectively achieve the thread synchronization you described. If you require thread synchronization for the two control loops, you would however still have to use semaphores, rendezvous', notifiers, and other built-in synch methods.
In the image there's an init function that opens two serial devices (purple wire) and passes them to the control loops, which both runs until an error (yellow-black wire) occurs. The errors from both are merged and passed to the teardown function that releases the serial devices. Notice that in this particular example the synchronization would occur at the end of program as long as there's at least one wire coming from each loop to the teardown function.
Similar functionality in a text based programming language would necessitate the use of more elaborate mechanisms, though some specialised language for parallel programming might help here.
I am currently running my UPPAAL simulator. My simulator stops running the code after a certain point. This point varies depending on the declaration i provide. But i would like to know generally when does the clock stop running? Is there something that triggers this?
I'm not sure if I interpret your question correctly, if I could read your model I may give you some precise advice.
Trying to guess what the problem is, I can say there are times when the Uppaal simulator takes infinitely many discrete steps (transitions) without increasing any of the clock variables.
The feeling is that "the clock is stopped", while the rest of the simulation is going on. In this case, the time is not actually stopped: Uppaal, among all possible paths, it is just exploring the one where clock does not evolve. If the simulator (or the model checker) can take infinitely many transitions without increasing the clock variables, that is an example of "Zeno path".
It is a responsibility of the person who writes the model to avoid the possibility of taking zeno paths.
If you are not sure your model is free of Zeno paths, you can use known methods for verifying that a Timed Automaton has no zeno paths (in Uppaal).
Another possibility is that the simulator stop running at all saying that there is a deadlock. In this case the problem is not that the clock stopped running, but that you arrived at a situation where all possible transitions are disabled (maybe because all possible guards are never enabled, or because all the possible target states of your enabled transitions have some time invariants that are false)
I am trying to make use of the ATMega16's timer0 to generate PWM pulses and output sound on a basic buzzer..
But i am facing a problem figuring out how i can be able to change the frequency of the waves im creating (to generate different notes)
I saw on the datasheet that with the timer0 you can use ICR for TOP values and that way you can change the frequency and with OCR you'll be able to change the duty cycle..
Is there a similar way but on either timer0 or timer2 ?
I am already using timer1 to control something else so i'm wondering if i have to start over :(
Thanks in advance,
Any idea is appreciated
Generally, when "running out of" timers, simple software routines based on timer interrupts will take you pretty far.
For example, using one of the timer compare interrupts you could easily generate almost all frequencies:
In the timer compare ISR just toggle the respective output pin and (let the timer be) reset to 0. The set compare value determines the generated frequency in terms of fractions of the timer's frequency.
There are many more elaborate ways to use a limited number of available timers to perform a lot of timer tasks at the same time. It is basically all just based on thoughtfully used ISRs.