I am trying to implement a module in my project for which i need the final value to be stable for a while, hence implemented as below. both of them are showing the same result in simulation. will the tool generate same hardware or different one?
always #(posedge clk) begin
if(en)
count <= count + 1;
else
begin
a <= count;
count <= 0;
end
if(count == 0) b <= a;
end
what is the difference between above coding style and the one below? Does it make any difference while synthesis?
always #(posedge clk) begin
if(en)
count <= count + 1;
else
begin
a <= count;
count <= 0;
end
end
always #(posedge clk) begin
if(count == 0)
b <= a;
end
And I am using Vivado 2015.4 tool for synthesis.
It will generate the same hardware output. It doesn't matter if you split clocked statements into one or multiple always-statements, as long as they are functionally identical.
will the tool generate same hardware or different one?
Click "open elaborated design" in Vivado and see for yourself!
But what you'll find is: they're equivalent. No difference whatsoever.
Related
I have tried writing a small verilog module that will find the maximum of 10 numbers in an array. At the moment I am just trying to verify the correctness of the module without going into specific RTL methods that will to do such a task.
I am just seeing a a couple of registers when I am synthesizing this module. Nothing more that that. Ideally the output should be 7 which is at index 4 but I am seeing nothing neither on FPGA board or in the test bench. What I am doing wrong with this ?
module findmaximum(input clk,rst,output reg[3:0]max, output reg[3:0]index);
reg [3:0]corr_Output[0:9];
always#(posedge clk or posedge rst)
if(rst)
begin
corr_Output[0]=0;
corr_Output[1]=0;
corr_Output[2]=0;
corr_Output[3]=0;
corr_Output[4]=0;
corr_Output[5]=0;
corr_Output[6]=0;
corr_Output[7]=0;
corr_Output[8]=0;
corr_Output[9]=0;
end
else
begin
corr_Output[0]=0;
corr_Output[1]=0;
corr_Output[2]=0;
corr_Output[3]=0;
corr_Output[4]=7;
corr_Output[5]=0;
corr_Output[6]=0;
corr_Output[7]=0;
corr_Output[8]=0;
corr_Output[9]=0;
end
integer i;
always#(posedge clk or posedge rst)
if(rst)
begin
max=0;
index=0;
end
else
begin
max = corr_Output[0];
for (i = 0; i <= 9; i=i+1)
begin
if (corr_Output[i] > max)
begin
max = corr_Output[i];
index = i;
end
end
end
endmodule
Looking are your code, the only possible outputs are max=0,index=0 and a clock or two after reset max=7,index=4. Therefore, your synthesizer is likely optimizing the code with equivalent behavior with simpler logic.
For your find max logic to be meaningful, you need to change the values of corr_Output periodically. This can be done via input writes, LFSR (aka pseudo random number generator), and or other logic.
Other issues:
Synchronous logic (updated on a clock edge) should be assigned by with non-blocking (<=). Combinational logic should be assigned with blocking (=). When this guideline is not followed there is a risk of behavior differences between simulation and synthesis. In the event you need to compare with intermediate values (like your original max and index), then you need to separate the logic into two always blocks like bellow. See code bellow.
Also, FPGAs tend to have limited asynchronous reset support. Use synchronous reset instead by removing the reset from the sensitivity list.
always#(posedge clk) begin
if (rst) begin
max <= 4'h0;
index <= 4'h0;
end
else begin
max <= next_max;
index <= next_index;
end
always #* begin
next_max = corr_Output[0];
next_index = 4'h0;
for (i = 1; i <= 9; i=i+1) begin // <-- start at 1, not 0 (0 is same a default)
if (corr_Output[i] > next_max) begin
next_max = corr_Output[i];
next_index = i;
end
end
end
How to fix multiple driver , default value and combinational loop problems in the code below?
always #(posedge clk)
myregister <= #1 myregisterNxt;
always #* begin
if(reset)
myregisterNxt = myregisterNxt +1;
else if(flag == 1)
myregister = myregister +2;
end
right there are at least 3 issues in your code:
you are driving myregister within 2 different always blocks. Synthesis will find multiple drivers there. Simulation results will be unpredictable. The rule: you must drive a signal within a single always block.
you ave a zero-delay loop over myregisterNxt = myregisterNxt +1. Since you are using a no-flop there, it is a real loop in simulation and in hardware. You need to break such loops with flops
#1 delay is not synthesizable and it is not needed here at all.
You have not described what you were trying to build and it is difficult to figure it out from our code sample. In general, reset is used to set up initial values. So, something like the following could be a template for you.
always #(posedge clk) begin
if (reset)
myregister <= 0;
else
myregister <= myregister + increment;
end
always #* begin
if (flag == 1)
increment = 1;
else
increment = 2;
end
the flop with posedge clk and nonblocking assignments will not be in a loop.
I have two push buttons (using Basys2 rev C board) and I want to increment a register (counter) when I push one of them. I used this:
always #( posedge pb1 or posedge pb2 )
begin
if(count2==9) count2=0;
else count2= count2+1;
end
but when I implemented it (using ISE 9.2), an error appeared:
The logic for does not match a known FF or Latch template.
However when I tried it using just one event (posedge pb1), it worked.
So why did that happen?
The error message means that the target technology (I am guessing in your case is an FPGA or CPLD) doesn't have the physical circuit required to implement the functionality you described with this behavioural code.
One of the important things to consider when writing synthesizable RTL (verilog or VHDL) is you are describing an electronic circuit. You should understand what real world logic you are trying implement (combinatorial logic, registers) before you start coding. In this case, you are describing a register with two separate clocks--something that doesn't exist in any FPGA or ASIC library I've seen. If you can't figure out what you're trying to implement, the chances are the synthesizer can't either.
In other words, not everything you can describe in Verilog can be translated into an actual circuit.
The solution depends on what you want to do - if you require that the counter increments on both pb1 and pb2 rising edges, irrespective of the other pbs state, I would look into solutions which use another (independent) clock (clk in the code below) - something like this:
reg old_pb1, old_pb2;
always # (posedge clk) begin
if (old_pb1 == 0 && pb1 == 1)
if(count2==9) count2 = 0;
else count2 <= count2 + 1;
if (old_pb2 == 0 && pb2 == 1)
if(count2==9) count2 = 0;
else count2 <= count2 + 1;
old_pb1 <= pb1;
old_pb2 <= pb2;
end
If you have no other clock, you could also combine both input signals like in this example:
wire pbs = pb1 | pb2;
always # (pbs) begin
if(count2==9) count2 <= 0;
else count2 <= count2 + 1;
end
Another option would be to use independent counters for the inputs:
always # (posedge pb1)
begin
if(count_pb1==9) count_pb1 <= 0;
else count_pb1 <= count_pb1 + 1;
end
always # (posedge pb2)
begin
if(count_pb2==9) count_pb2 <= 0;
else count_pb2 <= count_pb2 + 1;
end
wire [4:0] count2 = count_pb1 + count_pb2;
All options have their own restrictions, limitations and drawbacks, therefore it depends heavily on what you want to do. Corner cases matter.
Note that I put these example codes together without testing them - please let me know in a comment if you are having trouble with any of them and I look into it.
I currently have this code(below) for a debouncer for a button on an fpga, however I am getting an error that says "Multiple event control statements in one always/initial process block are not supported in this case." whenever I try to synthesize the desgin. The line that causes the problem is the #(posedge clk) but I'm wondering how exactly to replace this logic. What I essentially require is always # (quarter & posedge clk)as the sensitivity list for the first always block but this does not work either. I am fairly new to the language so I'm still working out a few syntax kinks.Snippet of Code is below:
always #(quarter)
begin
#(posedge clk)
begin
if (quarter != new) begin new <= quarter; count <= 0; end
else if (count == DELAY) cleanq <= new;
else count <= count+1;
end
end
instead of always
#(posedge event1)
#(posedge event2)
create aflag (1bit reg) event2done : reg event2done; initial event2done=0;
always#(posedge event1)
begin if (!event2done & event 2)
// event2done=1; + type ur code
else if(event2done & !event 2)
event2done =0; end
pseudo code:
always#(something1)
#(something2)
do something
Look in the comments to see explanation as to why this isn't synthesizable
always #(posedge clk)
/* over here you'll have to set the default values
for everything that's being changed in this always block,
you'll otherwise generate latches. Which is likely
not what you want */
begin
if (quarter != new) begin new <= quarter; count <= 0; end
else if (count == DELAY) cleanq <= new;
else count <= count+1;
end
I don't have access to my verilog rig at the moment so I can't confirm the syntax correctness
I am trying to read the values of memory after 5 cycles into an output register in verilog. How do I do that?
For example if i have a code which looks like this,
reg[31:0] mem[0:5];
if(high==1)
begin
newcount1<=count2;
mem[i]<=newcount1;
i<=i+1;
count2=0;
end
After the 5 cycles of operation whatever mem values i get, how do i read them in another output register? and can i perform averaging operation on those 5 cycles? and get a nominal value?
Say Your Memory Data Out is mem_data and you want it Read out in mem_data_out with Latency of 5 Cycles.
parameter MDP_Latency = 4;
reg [31:0] mem_data_out;
reg [31:0] [MDP_Latency - 1 : 0] mem_data_out_temp;
always#(posedge clk) begin
if(!reset) begin
for(int i = 0; i < MDP_Latency; i ++)
begin
mem_data_out <= 'd0;
mem_data_out_temp[i] <= 'd0;
end
end
else
begin
for(int i = 0; i < MDP_Latency; i ++)
begin
if(i == 0)
begin
mem_data_out_temp[i] <= mem_data;
end
else
begin
mem_data_out_temp[i] <= mem_data_out_temp[i - 1];
end
end
mem_data_out <= mem_data_out_temp[MDP_Latency];
end
end
`
Lets have a look at the posted code:
reg[31:0] mem[0:5];
if(high==1)
begin
newcount1<=count2;
mem[i]<=newcount1;
i<=i+1;
count2=0;
end
The lack of indentation makes it hard to read, i is not declared. The memory is actually 6 locations, 0 to 5.
You have conditionals and assignment not insides and initial or always block.
I am not sure what you are doing with count2 but mixing blocking and non-blocking is considered bad practise, it can be done but you must be really careful to not cause RTL to gates mismatch.
User1932872 Has posted an answer using for loops it looks like a valid answer but I think loops at this stage over complicate learning and understanding what you are creating in HDLs. While learning I would avoid such features and only uses them once comfortable with the whole flow.
reg[31:0] mem[0:4]; //5 Locations
always #(posedge clk) begin //Clked process assignmnets use non-blocking(<=)
mem[0]<=newcount1;
mem[1]<=mem[0];
mem[2]<=mem[1];
mem[3]<=mem[2];
mem[4]<=mem[3];
end
With this structure we can see the pipeline of data though mem[0] to mem[4]. We are implying 5 flip-flops where the output of the first drives data into the next. A combinatorial sum of them all could be:
reg [31+4:0] sum; //The +4 allows for bitgrowth you may need to truncate or limit.
always #* begin // Combinatorial use blocking (=)
sum = mem[0] + mem[1] + mem[2] + mem[3] + mem[4];
end