I want to convert a SystemVerilog assertion with delay into an invarspec of a formal verifier. The synthesizer gives syntax error for ##1 in the code line below.
assert property ( ( req1 == 0 ) ##1( req1 == 1 ) ##1 !( req2 == 1 ) || ( gnt1 == 0 ) );
There are several properties that are to be verified and have delays. I am currently trying to convert them into formal (SMV) model specifications using a synthesizer which works fine for the properties not involving delays. Can I model delay for this formal verifier tool ? If so, how?
One approach is to explicitly model the delayed version of the signals in Verilog, and then you can use an assertion that has no time dependency.
For your example:
assert property ( ( req1 == 0 ) ##1( req1 == 1 ) ##1 !( req2 == 1 ) || ( gnt1 == 0 ) );
becomes:
reg req1_r,req1_rr;
always #(posedge clk) begin
req1_rr <= req1_r;
req1_r <= req1;
end
assert property ( !(( req1_rr == 0 ) && ( req1_r == 1 ))
|| !( req2 == 1 ) || ( gnt1 == 0 ) );
Related
In Groovy, is there an elegant ( and clear ) way to check multiple objects for null ..example
def a = null
def b = null
def c = null
def d = null
// Is there a simpler ( more elegant ) version of this line of code
if ( a== null || b== null || c == null || d == null ) {
print "Null detected"
}
In Groovy, is there an elegant ( and clear ) way to check multiple objects for null
It may depend on your preference and what you find to be elegant, but the code you show there is idiomatic.
I am trying to run a testbench which was written for a neuromorphic chip named ODIN.
Irun this code in Xilinx ISE. I get some errors that do not make sense. here is a part of code:
$display("----- Starting verification of programmed SNN parameters");
assert(snn_0.spi_slave_0.SPI_GATE_ACTIVITY == 1'b1) else $fatal(0, "SPI_GATE_ACTIVITY parameter not correct.");
assert(snn_0.spi_slave_0.SPI_OPEN_LOOP == `SPI_OPEN_LOOP ) else $fatal(0, "SPI_OPEN_LOOP parameter not correct.");
assert(snn_0.spi_slave_0.SPI_SYN_SIGN == `SPI_SYN_SIGN ) else $fatal(0, "SPI_SYN_SIGN parameter not correct.");
assert(snn_0.spi_slave_0.SPI_BURST_TIMEREF == `SPI_BURST_TIMEREF ) else $fatal(0, "SPI_BURST_TIMEREF parameter not correct.");
assert(snn_0.spi_slave_0.SPI_OUT_AER_MONITOR_EN == `SPI_OUT_AER_MONITOR_EN ) else $fatal(0, "SPI_OUT_AER_MONITOR_EN parameter not correct.");
assert(snn_0.spi_slave_0.SPI_AER_SRC_CTRL_nNEUR == `SPI_AER_SRC_CTRL_nNEUR ) else $fatal(0, "SPI_AER_SRC_CTRL_nNEUR parameter not correct.");
assert(snn_0.spi_slave_0.SPI_MONITOR_NEUR_ADDR == `SPI_MONITOR_NEUR_ADDR ) else $fatal(0, "SPI_MONITOR_NEUR_ADDR parameter not correct.");
assert(snn_0.spi_slave_0.SPI_MONITOR_SYN_ADDR == `SPI_MONITOR_SYN_ADDR ) else $fatal(0, "SPI_MONITOR_SYN_ADDR parameter not correct.");
assert(snn_0.spi_slave_0.SPI_UPDATE_UNMAPPED_SYN == `SPI_UPDATE_UNMAPPED_SYN ) else $fatal(0, "SPI_UPDATE_UNMAPPED_SYN parameter not correct.");
assert(snn_0.spi_slave_0.SPI_PROPAGATE_UNMAPPED_SYN == `SPI_PROPAGATE_UNMAPPED_SYN) else $fatal(0, "SPI_PROPAGATE_UNMAPPED_SYN parameter not correct.");
assert(snn_0.spi_slave_0.SPI_SDSP_ON_SYN_STIM == `SPI_SDSP_ON_SYN_STIM ) else $fatal(0, "SPI_SDSP_ON_SYN_STIM parameter not correct.");
I get this error for each line:
Syntax error near "else".
In our simple case for simulation with verilog v2k you can use $display to print a message:
always #* begin
$display("----- Starting verification of programmed SNN parameters");
if(snn_0.spi_slave_0.SPI_GATE_ACTIVITY != 1'b1)
$display("fatal: SPI_GATE_ACTIVITY parameter not correct.");
...
end
To sum it up, Xilinx ISE does not support SystemVerilog, so we can not use assertion.
To run this testbench I have to use Xilinx Vivado. Another way is to implement some function equivalent to assertion in verilog. Look at these answers at "Assert statement in Verilog"
I'm trying to make a calculator in Haxe, it is almost done but have a bug. The bug is happening every time that some part of the equation result in 0.
This is how I concatenate the numbers and put i the array number, the cn is the variable used to receive the digit and transform in a number, the ci is a specific counter to make the while work well and the c is the basic counter that is increased to a background while used to read the array (input) items:
var cn = '';
var ci = c;
if (input[c] == '-') {
number.push('+');
cn = '-';
ci ++;
}
while (input[ci] == '0' || input[ci] == '1' || input[ci] == '2' || input[ci] == '3' || input[ci] == '4' || input[ci] == '5' || input[ci] == '6' || input[ci] == '7' || input[ci] == '8' || input[ci] == '9' || input[ci] == '.') {
if(ci == input.length) {
break;
}
cn += input[ci];
ci++;
}
number.push(cn);
c += cn.length;
This is the part of the code used to calculate the addition and subtraction
for (i in 0 ... number.length) { trace(number); if (number[c] == '+') { number[c-1] = ''+(Std.parseFloat(number[c-1])+Std.parseFloat(number[c+1])); number.remove(number[c+1]); number.remove(number[c]); }
else {
c++;
}
}
Example:
12+13-25+1: When my code read this input, it transform in a array ([1,2,+,1,3,-,2,5,+,1]), then the code concatenate the numbers ([12,+,13,-,25,+,1]) and for lastly it seeks for the operators(+,-,* and /) to make the operation (ex: 12+13), substituting "12" for the result of the operation (25) and removing the "+" and the "13". This part works well and then the code does 25-25=0.
The problem starts here because the equation then becomes 0+1 and when the code process that what repend is that the 0 vanish and the 1 is removed and the output is "+" when the expected is "1".
remove in this case uses indexOf and is not ideal, suggest using splice instead.
number.splice(c,1);
number.splice(c,1);
https://try.haxe.org/#D3E38
I have a project in verilog where I'm keeping track of the date. I have the following code to handle the different length of months, unless I am mistaken I can combine these all by oring each condition and just having one if statement. This however will result in using 1 more LE. Why?
if( ( months == 4 || months == 6 || months == 9 || months == 11 ) && days == 31 && set_state == 0 ) begin
months = months + 1;
days = 1;
end
else if( months == 2 && years[1:0] == 0 && days == 30 && set_state == 0 ) begin
months = months + 1;
days = 1;
end
else if( months == 2 && years[1:0] != 0 && days == 29 && set_state == 0 ) begin
months = months + 1;
days = 1;
end
else if( days == 32 ) begin
months = months + 1;
days = 1;
end
EDIT: This is what uses the additional LE
if( ( ( months == 4 || months == 6 || months == 9 || months == 11 ) && days == 31 && set_state == 0 ) ||
( months == 2 && years[1:0] == 0 && days == 30 && set_state == 0 ) ||
( months == 2 && years[1:0] != 0 && days == 29 && set_state == 0 ) ||
( days == 32 ) ) begin
months = months + 1;
days = 1;
end
The two statements are logically equivalent using the following Boolean law:
A | (~A & B) = A | B
I think it has to do with the synthesis tool logic minimization algorithm that does not synthesize exactly the same circuits, although they are logically equivalent.
I have translated the following code using ternary. However, I knew there was something wrong with it. Can someone please point me into the right direction?
ForwardA = 0;
ForwardB = 0;
//EX Hazard
if (EXMEMRegWrite == 1) begin
if (EXMEMrd != 0)
if (EXMEMrd == IDEXrs)
ForwardA = 2'b10;
if (EXMEMrd == IDEXrt && IDEXTest == 0)
ForwardB = 2'b10;
end
//MEM Hazard
if (MEMWBRegWrite == 1) begin
if (MEMWBrd != 0) begin
if (!(EXMEMRegWrite == 1 && EXMEMrd != 0 && (EXMEMrd == IDEXrs)))
if (MEMWBrd == IDEXrs)
ForwardA = 2'b01;
if (IDEXTest == 0) begin
if (!(EXMEMRegWrite == 1 && EXMEMrd != 0 && (EXMEMrd == IDEXrt)))
if (MEMWBrd == IDEXrt)
ForwardB = 2'b01;
end
end
end
ForwardA = (MEMWBRegWrite && MEMWBrd != 0 && (!(EXMEMRegWrite == 1 && EXMEMrd != 0 && (EXMEMrd == IDEXrs))) && (MEMWBrd == IDEXrs)) ?
2'b01 : ((EXMEMRegWrite && EXMEMrd != 0 && EXMEMrd == IDEXrs) ? 2'b10 : 0);
ForwardB = (IDEXTest == 0 && MEMWBRegWrite && MEMWBrd != 0 && (!(EXMEMRegWrite == 1 && EXMEMrd != 0 && (EXMEMrd == IDEXrt))) && (MEMWBrd == IDEXrs)) ?
2'b01 : ((EXMEMRegWrite && EXMEMrd != 0 && EXMEMrd == IDEXrt && IDEXTest == 0) ? 2'b10 : 0);
Surprisingly enough, I'm going to risk downvotes and tell you that the right direction is to leave your code in its relatively readable state.
I suspect the only thing you could do that would be worse would be to do it as a regular expression or convert it to inline assembly :-)
The fact that it's not converting easily should tell you something about the wisdom in what you're attempting.
Based on your comment elsewhere:
This is verilog and therefore I need to do it in ternary and can't have an if else, otherwise I would need an always block before and I don't want that... I want the remaining to be 0 if none of the conditions in the if else above is satisfied
Well, if you must do it, against my advice (and I'm not alone here in offering this advice), here's the method you should use (I have no idea what an "always block" even is so I'm not qualified to argue the point with you).
Since your current code is setting ForwardA and ForwardB to values then only changing them under certain conditions, you can transform that into a ternary by reversing the order. That's because, in your if version, later code takes precedence but earlier code takes precedence in the ternary.
Find out under what circumstances ForwardA and ForwardB are set in reverse order and reconstruct those conditions.
Here's your original code, compressed a bit. I've also changed your 2'b10 things into 2'b10' so we still get nice formatting in the SO rendering engine - don't forget to change them back.
ForwardA = 0;
ForwardB = 0;
if (EXMEMRegWrite == 1) begin
if (EXMEMrd != 0)
if (EXMEMrd == IDEXrs)
ForwardA = 2'b10';
if (EXMEMrd == IDEXrt && IDEXTest == 0)
ForwardB = 2'b10';
end
if (MEMWBRegWrite == 1) begin
if (MEMWBrd != 0) begin
if (!(EXMEMRegWrite == 1 && EXMEMrd != 0 && (EXMEMrd == IDEXrs)))
if (MEMWBrd == IDEXrs)
ForwardA = 2'b01';
if (IDEXTest == 0) begin
if (!(EXMEMRegWrite == 1 && EXMEMrd != 0 && (EXMEMrd == IDEXrt)))
if (MEMWBrd == IDEXrt)
ForwardB = 2'b01';
end
end
end
You can see B is set in three places. It's set to 2'b01 in the bottom if, 2'b10 in the top one and 0 at the start. Converting the conditions:
ForwardB = ((MEMWBRegWrite == 1) &&
(MEMWBrd != 0) &&
(IDEXTest == 0) &&
(!(EXMEMRegWrite == 1 && EXMEMrd != 0 && (EXMEMrd == IDEXrt))) &&
(MEMWBrd == IDEXrt))
? 2'b01'
: ((EXMEMRegWrite == 1) &&
(EXMEMrd != 0) &&
(EXMEMrd == IDEXrt && IDEXTest == 0))
? 2'b10'
: 0;
Similarly for A:
ForwardA = ((MEMWBRegWrite == 1) &&
(MEMWBrd != 0) &&
(!(EXMEMRegWrite == 1 && EXMEMrd != 0 && (EXMEMrd == IDEXrs))) &&
(MEMWBrd == IDEXrs))
? 2'b01'
: ((EXMEMRegWrite == 1) &&
(EXMEMrd != 0) &&
(EXMEMrd == IDEXrs))
? 2'b10'
: 0;
Now the theory behind that is good but I wouldn't be the least bit surprised if I'd made an error in the transcription, or if Verilog just threw its hands up in disgust, picked up its ball, and trotted off home :-)
Can I at least suggest, if you must follow this path, you both:
try to leave the ternary expressions at least a little readable, with all that nice white space and multiple lines; and
keep the original code in a comment so at least you can go back to it if you have problems or want to change the logic?
Seriously, you'll thank me in six months time when you're looking over this again, trying to figure out what on Earth you were thinking :-)
You don't need to do this. Stick the code in an 'always #*' block, and declare anything you're assigning to as 'reg'.
reg [1:0] ForwardA;
reg [1:0] ForwardB;
always #(*) begin
// Your combo logic here..
end
First don't do it! there's no point, in doing so. It doesn't compile to better code and is less readable, as you noticed in your tries to correct it. If you need it as an expression it would be better to code it as an inline function.
Well, assuming that you insist on keeping it in ternary form for whatever reason, your readability would go up considerably if you'd just format it correctly.
const bool cond1 = MEMWBRegWrite && MEMWBrd != 0 &&
!(EXMEMRegWrite == 1 && EXMEMrd != 0 && EXMEMrd == IDEXrs) &&
MEMWBrd == IDEXrs;
ForwardA = cond1
? 2'b01
: ((EXMEMRegWrite && EXMEMrd != 0 && EXMEMrd == IDEXrs) ? 2'b10 : 0);
const bool cond2 = IDEXTest == 0 &&
MEMWBRegWrite && MEMWBrd != 0 &&
!(EXMEMRegWrite == 1 && EXMEMrd != 0 && EXMEMrd == IDEXrt) &&
MEMWBrd == IDEXrs;
ForwardB = cond2
? 2'b01
: ((EXMEMRegWrite && EXMEMrd != 0 && EXMEMrd == IDEXrt && IDEXTest == 0) ? 2'b10 : 0);
Now, that code is formatted as if it were C++ rather than whatever you're actually using, but it becomes much easier to figure out what's going on.
However, I would point out that your if-statements can't possibly match your ternary expressions. Your if statements have no else clause, and ternary expressions always have else clauses. However, since your question doesn't even make it entirely clear whether you're trying to convert the if-statements into ternary expressions or the ternary expressions into if-statements, it's a bit hard to give you exactly what you want.
EDIT: Ternary expressions always have both an if and an else clause. You cannot directly turn an if statement without an else clause into a ternary because you wouldn't have the else portion of the ternary. Now, you can pull some tricks in some cases if you need to, like setting a variable to itself. For instance,
ForwardA = cond1 ? newValue : FordwardA;
You're basically saying not to change the value in the else clause - but that's assuming that you're assigning the result to a variable. The more complicated the expression, the harder it is to pull that sort of trick, and the more convoluted the code becomes when you do. Not to mention, depending on what optimizations that the compiler does or doesn't do, it could be assigning the variable to itself, which isn't terribly efficient.
Generally-speaking, translating if-statements with no else clauses into ternary expressions is a bad idea. It can only be done by pulling tricks rather than directly saying what you mean, and it just complicates things. And this code is complicated enough as it is.
I'd advise not using a ternary here unless you really need it. And if you do, at least break down the expression. Even if your ternary expression were correct, it's much harder to read than the if-statements.
EDIT 2: If you really do need this to be a ternary expression, then I'd advise that you sit down and figure out the exact conditions under which ForwardA should be what set of values and create a ternary expression based on that rather than trying to directly convert the if-statements that you have (and the same for ForwardB). Your if-statments are not only deciding what value to assign to each variable, but which variable to assign that value to, and that complicates things considerably.
In other languages (I don't know about verilog), you can use a ternary expression for choosing which variable to assign the value to in addition to whatever you're doing on the right side of the expression, but that's getting really complicated. It might be best to create a temporary which holds the value which is to be assigned and a separate ternary to determine which variable to assign it to.
Not knowing verilog, I really don't know what you can and can't do with if-statements and ternary expression, but I would think that there's got to be a better way to handle this than using a ternary. Maybe not, but what you're trying to do is very difficult and error-prone.