Is there any tool/application available online which helps me to check the synthesis output of the RTL written?
Example: I have written some RTL code(In verilog) and want to check
-> If it is synthesize-able or not?
-> Netlist RTL has generated.
Might this meet your needs?
http://www.plunify.com/
Some words from the website to make this answer long enough...
Plunify helps design teams manage and scale compute demands, providing
FPGA synthesis and place-and-route on a pay-as-you-use basis
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I have very poor verilog knowledge, but i need to convert Verilog project, containing some .v files and folders wth .v files to one large EDIF file for parcing.
Is there any easy way to do this?
I have found iverilog tool, but not sure how to convert all project with subfolders at once.
Thank you!
EDIF (Electronic Design Interchange Format) is a vendor-neutral format in which to store Electronic netlists and schematics. https://en.wikipedia.org/wiki/EDIF .
Verilog is a Hardware Description Language, which can describe hardware at a higher, behavioural level of abstraction.
So, in general at least, the two are not compatible. So, in general, you will need to convert your Verilog to gate-level in order for it to be suitable for EDIF. The tool that converts Verilog to gate-level is a logic synthesiser and most, if not all, logic synthesisers will be able to output your netlist as an EDIF file.
So,
if your Verilog is not already gate-level, you will need a logic synthesiser. If you're doing an FPGA design, that will be your FPGA tool: Quartus, Vivado etc.
if your Verilog is already gate-level, then there may be other, more basic, tools that convert from one to another; I don't know. But, if your Verilog is already gate-level, a logic synthesiser will also be able to do the conversion.
In FPGA programming, what is the point of using the create_clock command in the XDC (or UCF) file? Let's say I have a clock port CLK that is assigned to a physical pin (which is my clock), in the XDC (or UCF) file. Why can't I just go ahead and use this CLK pin in my top level HDL? Why do I need to add something like this:
create_clock -name sys_clk_pin -period "XXX" [get_ports "CLK"]
Also, let's say I have a main clock "CLK" and some other clocks which I generate in HDL. Do I have to use "create_clock" for all the minor clock in XDC too?
I don't get this whole "create_clock" thing. Any help or direction is much appreciated.
Thanks
Design constraints, as the name suggests, are used in order to define additional constraints of your design, which can't be captured from HDL description.
Lets take create_clock command as an example. You specified the clock pin in your HDL description, why isn't this enough? The reason is that clock signal is not a usual signal - it is used as a reference signal by a synchronous logic (flip-flops).
I suppose you're familiar with "propagation delay" (through logic gates) concept. You want to make sure that all signals originating at one flop and sampled at the other will be able to propagate during a single clock cycle. Now, the total propagation delay you can know right after synthesis because each logic gate in FPGA has associated propagation delay (just sum these up). But how your analysis tools know what is the maximal allowed propagation delay? You do not specify these constraints in HDL, right? This is one of the cases where the frequency you specified with create_clock command will be used - it will be converted to period, and an analysis tool will warn you if any of the combinatorial paths in your design takes longer to propagate than clock's period.
The above example describes one of the actions performed by Static Timing Analysis (STA) tools in which "design constraints" are employed.
Another kind of tools which make extensive use of design constraints is Clock Domain Crossing (CDC) tools. These tools employed in designs containing more than one clock. The CDC concepts are described brilliantly here
In case you take one clock and generate another one from it (clock divider for example) you want to make CDC tool aware of this, because the fact that these clocks are related is important. Your way to inform CDC tool that the clocks are related is to use create_generated_clock constraint.
NOTE: the above examples are basic and by no means comprehensive.
Can anyone provide sample pseudocode or share some existing link that has sample code.
Like for example I have a mix audio of 1kHz or 2kHz or 8kHz or so, and I want to boost certain frequencies like 1kHz only in real-time.
Reading some DSP books and resources confuses me.
You just need to design and implement a suitable digital filter. This is a large and complex subject area though, so you won't get a simple answer here. Probably the best thing as a first step would be to read a good introductory book on DSP, e.g. Understanding DSP by Rick Lyons, which is a very good for beginners as it's not too heavy on the math and has a more practical bent than most such introductory DSP books.
For this particular application though what you are trying to do is similar to implementing a graphic equalizer, and there are many pointers to how to implement this kind of thing if you use e.g. "graphic equalizer" as a search term.
There's a lot of math behind digital filtering. Sorry, I think it is important to at least understand basic filters (like those used in electronics). If you don't want to go through the basics: best to get an audio graphics equaliser where you can play with the (virtual) sliders. If you want to implement a very specific filter, please read on.
Real time: depends on your computing platform. If this is a small micro (like AVR, Microchip PIC,..) you'll need an efficient algorithm. This is likely a IIR band pass filter. The equivalent of a graphics equaliser consists of multiple band pass filters, all summed together. See http://en.wikipedia.org/wiki/Infinite_impulse_response
A more computing intensive algorithm uses FIR filters. In that case you can also control the phase of the filtered signal. http://en.wikipedia.org/wiki/Finite_impulse_response
If you find an algorithm (i.e. IIR), you'll need to calculate the coefficients. The algorithm is simple, calculating the coefficients is not.
I found a book matching your question: Audio digital signal processing in real time
I browsed through it; it seems to have the right answers.
Can anyone tell me how to write a verilog code for DWT of an image and download in to fpga.
Actually my project is to write a verilog code to perform discrete wavelet transform of a medical image, can anyone frame the logic or if have the code can you send me, please
I am using xilinx virtex 2 pro..
This one is in VHDL instead of Verilog, but might still provide at least some inspiration.
Generally FPGA's come with software for programming them. Depending on manufacturer those packages are different. But most of FPGA manufacturers(Xilinx, Altera, etc) ship tools to program their chips.
Besides that there are few 3rd party tools:
http://www.synopsys.com/Solutions/EndSolutions/FPGASolution/Pages/default.aspx
http://www.aldec.com/Products/default.aspx
Can anyone tell me how to write a verilog code for DWT of an image and download in to fpga.
Actually my project is to write a verilog code to perform discrete wavelet transform of a medical image, can anyone frame the logic or if have the code can you send me, please
I am using xilinx virtex 2 pro..
This one is in VHDL instead of Verilog, but might still provide at least some inspiration.
Generally FPGA's come with software for programming them. Depending on manufacturer those packages are different. But most of FPGA manufacturers(Xilinx, Altera, etc) ship tools to program their chips.
Besides that there are few 3rd party tools:
http://www.synopsys.com/Solutions/EndSolutions/FPGASolution/Pages/default.aspx
http://www.aldec.com/Products/default.aspx