EDIT: I tried out the methods mentioned below: I set my interface to wires instead of logic, and I drive 'Z from the driver that wants to relinquish control of the signal so that the other driver can take over. Still doesn't work as I see u_slave_dut not being driven from my interface. Any clues on what is wrong? My working example: https://www.edaplayground.com/x/4SSP
I am writing a testbench for a top-level module that has a number of sub-modules. I want to instantiate an interface and hook it up to one of my sub-modules, say my_submodule. Easy enough, and I can see my interface pins toggling when my_submodule pins are toggled. This makes for great observation.
Next, I decided I wanted to be able to toggle the pins myself from my interface (using a task). I realize this leads to 2 drivers on the same bus. So, is there a way for me to do this?
I created a small example of edaplayground to experiment, and here I see that none of my writes from my task in the interface actually toggle the pins on u_slave_dut. Also, I get no warnings from the compiler which bothers me too.
My working example is here: https://www.edaplayground.com/x/5fcP
testbench.sv
`include "my_interface.sv"
module tb;
bit clk = 1'b1;
bit control = 1'b0;
initial begin
forever begin
#5 clk = ~clk;
end
end
my_interface my_vif(clk);
assign my_vif.addr = (control)? tb.u_top.u_slave_dut.i_addr : 'hz;
assign my_vif.wdata = (control)? tb.u_top.u_slave_dut.i_wdata : 'hz;
assign my_vif.write = (control)? tb.u_top.u_slave_dut.i_write : 'hz;
top u_top(.clk(clk));
initial begin
#80 my_vif.master_write_something;
#160 $finish;
end
initial begin
$dumpfile("dump.vcd");
$dumpvars(0);
end
endmodule
interface.sv
interface my_interface(input clk);
logic [3:0] addr;
logic write;
logic [3:0] wdata;
logic [3:0] rdata;
logic resp;
clocking master_cb #(posedge clk);
input resp, rdata;
output addr, write, wdata;
endclocking
clocking slave_cb #(posedge clk);
input addr, write, wdata;
output resp, rdata;
endclocking
task master_write_something;
#(master_cb);
master_cb.write <= 1'b1;
#(master_cb);
master_cb.wdata <= 3'b101;
master_cb.addr <= 3'b111;
#(master_cb);
master_cb.write <= 1'b0;
endtask
task slave_write_something;
#(slave_cb);
slave_cb.resp <= 1'b1;
#(slave_cb);
slave_cb.rdata <= 3'b101;
#(slave_cb);
slave_cb.resp <= 1'b0;
slave_cb.rdata <= 3'b000;
endtask
endinterface
design.sv
module slave_dut (
input clk,
input [3:0] i_addr,
input [3:0] i_wdata,
input i_write,
output o_resp,
output [3:0] o_rdata
);
reg o_resp_reg;
reg [3:0] o_rdata_reg;
initial begin
o_resp_reg <= 1'b0;
o_rdata_reg <= 'h0;
end
always #(posedge clk) begin
if (i_write == 1'b1) begin
o_resp_reg <= 1'b1;
o_rdata_reg <= i_wdata;
end
else begin
o_resp_reg <= 1'b0;
o_rdata_reg <= 'h0;
end
end
assign o_resp = o_resp_reg;
assign o_rdata = o_rdata_reg;
endmodule : slave_dut
module master_dut (
input clk,
output [3:0] o_addr,
output [3:0] o_wdata,
output o_write,
input i_resp,
input [3:0] i_rdata
);
reg [3:0] o_addr_reg;
reg [3:0] o_wdata_reg;
reg o_write_reg;
initial begin
o_addr_reg <= 'h0;
o_wdata_reg <= 'h0;
o_write_reg <= 'h0;
repeat (2) #(posedge clk);
o_addr_reg <= 'hF;
o_wdata_reg <= 'hB;
o_write_reg <= 1'b1;
#(posedge clk);
o_addr_reg <= 'h0;
o_wdata_reg <= 'h0;
o_write_reg <= 'h0;
repeat (2) #(posedge clk);
o_addr_reg <= 'h4;
o_wdata_reg <= 'hD;
o_write_reg <= 1'b1;
#(posedge clk);
o_addr_reg <= 'h0;
o_wdata_reg <= 'h0;
o_write_reg <= 'h0;
end
assign o_addr = o_addr_reg;
assign o_wdata = o_wdata_reg;
assign o_write = o_write_reg;
endmodule : master_dut
module top(input clk);
wire [3:0] addr;
wire [3:0] wdata;
wire write;
wire resp;
wire [3:0] rdata;
master_dut u_master_dut (
.clk(clk),
.o_addr(addr),
.o_wdata(wdata),
.o_write(write),
.i_resp(resp),
.i_rdata(rdata)
);
slave_dut u_slave_dut (
.clk(clk),
.i_addr(addr),
.i_wdata(wdata),
.i_write(write),
.o_resp(resp),
.o_rdata(rdata)
);
endmodule
Any idea where I am going wrong?
I believe the one simulator you chose to run the simulator on does not give any warnings or errors. Any other simulator will correctly give the errors about mixing continuous assignments with procedural assignments from the clocking block.
If you are going to have the same signal driven from two different places, you need to deal with that by using a wire instead of a variable. You also need to turn off one of the drivers by setting it to high-impedance ('z), so the other driver can control the signal. This needs to be done regardless of whether the two drivers are within your design or between the design and testbench. I wrote a DVCon paper a few years ago that explains this in more detail.
As Dave explained, it is the only way to control the multi driver nets by enabling only one driver to drive the net at a time. And from hardware point of view as well, only one driver should drive any wire at a time.
This can be achieved in your design by using additional reg.
Please refer the following code.
module tb;
bit clk = 1'b1;
reg control = 1'b1;
initial begin
forever begin
#5 clk = ~clk;
end
end
my_interface my_vif(clk);
assign my_vif.addr = (control)? tb.u_top.u_slave_dut.i_addr : 'hz;
assign my_vif.wdata = (control)? tb.u_top.u_slave_dut.i_wdata : 'hz;
assign my_vif.write = (control)? tb.u_top.u_slave_dut.i_write : 'hz;
top u_top(.clk(clk));
initial begin
#80 my_vif.master_write_something (control);
#160 $finish;
end
initial begin
$dumpfile("dump.vcd");
$dumpvars(0);
end
endmodule
// Interface Task
task master_write_something (ref reg x);
#(master_cb);
x = 1'b0;
master_cb.write <= 1'b1;
#(master_cb);
master_cb.wdata <= 3'b101;
master_cb.addr <= 3'b111;
#(master_cb);
master_cb.write <= 1'b0;
endtask
And the dump file is as follow.
Related
I am using Quartus Prime Lite 19.1.0.
module memory_address_register1 #(
parameter ADDR_WIDTH = 4
)(
input clk, rst, load,
input [ADDR_WIDTH-1:0] add_in,
output reg [ADDR_WIDTH-1:0] add_out
);
always #(posedge clk) begin
if (rst) begin
add_out <= 4'b0000;
end else if (load) begin
add_out <= add_in;
end else begin
add_out <= add_out;
end
end
endmodule
module mmr_tb();
reg clk, rst, load;
reg [3:0] add_in;
wire [3:0] add_out;
initial begin
clk <= 1'b0;
rst <= 1'b0;
load <= 1'b0;
end
memory_address_register1 mmr (.clk(clk), .rst(rst), .load(load), .add_in(add_in), .add_out(add_out));
always #10 clk = ~clk;
initial begin
#20 add_in <= 4'd2;
#10 add_in <= 4'd3;
load <= 1'b1;
#30 add_in <= 4'd6;
#10 load <= 1'b1;
end
endmodule
It the output (add_out) accurate? Should the output (add_out) at t=70.0ns be "6" or "7"?
If the expected output is "6", can anyone explain why is that?
img2: posedge clk output value from previous clk cycle
I ran the testbench using modelsim, and I am able to get the expected output I wanted (output on the exact clock edge), but is it expected?
https://imgur.com/a/M85zPKT
You have potential race conditions in your testbench code. You should drive all your inputs in the testbench the same way you drive them in the design:
Use nonblocking assignments (<=) instead of blocking assignments (=)
Use #(posedge clk) instead of # delays
This will guarantee that your inputs will be synchronous to the clock. This also assures that pulsewidths of your inputs are a multiple of the clock period. Some of your signals are half a period wide or 1.5 periods wide.
module mmr_tb();
reg clk, rst, load;
reg [3:0] add_in;
wire [3:0] add_out;
initial begin
clk <= 0;
rst <= 1;
load <= 0;
add_in <= 0;
repeat (2) #(posedge clk);
rst <= 0;
forever #(posedge clk) begin
add_in <= add_in + 1;
end
end
memory_address_register1 mmr (.clk(clk), .rst(rst), .load(load), .add_in(add_in), .add_out(add_out));
always #10 clk = ~clk;
initial begin
repeat (4) #(posedge clk); load <= ~load;
repeat (1) #(posedge clk); load <= ~load;
repeat (4) #(posedge clk); load <= ~load;
repeat (1) #(posedge clk); load <= ~load;
repeat (3) #(posedge clk); $finish;
end
endmodule
I am struggling to understand why the output flickers between 0 and 1, when the output should constantly remain 0 since the reduction OR gate of 000 is 0 not 1.
When I tried a different bit width, the problem suddenly disappeared. However, I would like to know what is going on rather than relying on randomness for correctness.
project_test .sv
`timescale 1ns/1ns
module project_test
( input logic clk, rst,
input logic in,
output logic [2:0] c
);
logic [2:0] out;
always#(posedge clk or posedge rst) begin
if(rst)
out <= 'b0;
else if(in) begin
if(|out)
out <= 'b0;
end
else
out <= out + 1'b1;
end
assign c = out;
endmodule: project_test
testbench.sv
`timescale 1ns/1ns
module testbench;
logic clk, rst;
logic in;
logic [2:0] c;
project_test project_test(
.clk(clk),
.rst(rst),
.in(in),
.c(c)
);
initial begin
clk = 0;
rst = 1;
in = 0 ;
#30
rst = 0;
#20;
in = 1;
#500;
rst=1;
#100ns;
$stop();
end
always#(clk) begin
#10ns clk <= !clk;
end
endmodule
Simulation output:
RTL viewer:
That is an improper way to generate a clock signal in the testbench. You should not have the clk signal in the sensitivity list because it keeps re-triggerring the always block. Your clock generator potentially adds events to the Verilog event queue, which can cause odd behavior. In fact, when I ran your code on the Cadence simulator, I did not see the clock toggling at all.
This is a more standard way to generate a clock:
always begin
#10ns clk = !clk;
end
You are using a very verbose implementation. Why can't you do something like below.
always#(posedge clk or posedge rst)
begin
if(rst)
out <= 'd0;
else
out <= (in) ? 'd0 : (out + 1'b1);
end
I am looking to create an AND gate which gets the result after a delay of lets say 10ns an my clock is 500 ps. How will i delay the assignment without using # delays ?
I have tried to make a counter which increments but how to model it so that it only starts when my input changes. Also the input won't change till the first output is evaluated and assigned. Initial Counter is 0 and lets say delay is 3'b111 so i want the counter to go from 1 to 3'b111 and then assign it to y. Inputs are a and b to the and gate.
always#(posedge clk)begin
if (!reset) begin y <=0; counter <=0; end
else begin
counter <= counter +1'b1;
if(counter==delay)begin
y <= a & b;
counter <=0;
end
end
Well if your clock cycle is 500 ps then you will need to count to a higher value to reach 10ns. I rewrote your code and also added a testbench for you to try. It's kind of sloppy, I usually write vhdl and not verilog. Hope this helps.
//Module
module count_and (
input clk,
input reset,
input a,
input b,
output reg y,
output reg [4:0] counter
);
reg ready;
always#(posedge clk)begin
if (!reset) begin
y <=0;
counter <=0;
ready <= 0;
end
else if (ready == 1'b1) begin
counter <= counter +1'b1;
if (counter==5'b10011) begin
y <= a & b;
counter <=0;
ready <= 0; //turn it off after passing to y
end
end
end
always #(a,b) begin
ready <= 1'b1;
end
endmodule
//TestBench
`timescale 1ps/1ps
module tb_count ();
reg a,b;
reg clk;
reg reset;
wire [4:0] counter;
wire y;
initial begin
clk = 1'b1;
reset = 1'b0;
a = 1'b0;
b = 1'b0;
end
always begin
reset <= #50 1'b1;
clk = #250 ~clk;
a <= #1000 1'b1;
b <= #1000 1'b1;
end
count_and count_and_inst (
.clk(clk),
.reset(reset),
.a(a),
.b(b),
.y(y),
.counter(counter)
);
endmodule
I am currently working on random number generation using Verilog. Sources have indicated that using Linear Feedback Shift Registers are one of the best ways to randomize MSBs. So I decided to code and testbench an LFSR. Snippet is below:
module lfsr_counter(clk, reset, ce, lfsr_done);
input clk, reset, ce;
output lfsr_done;
reg lfsr_done;
reg [10:0] lfsr;
initial lfsr_done = 0;
wire d0,lfsr_equal;
xnor(d0,lfsr[10],lfsr[8]);
assign lfsr_equal = (lfsr == 11'h359);
always #(posedge clk,posedge reset) begin
if(reset) begin
lfsr <= 0;
lfsr_done <= 0;
end
else begin
if(ce)
lfsr <= lfsr_equal ? 11'h0 : {lfsr[9:0],d0};
lfsr_done <= lfsr_equal;
end
end
endmodule
module testbench();
reg clk, reset, ce;
wire lfsr_done;
lfsr_counter dut(clk, reset, ce, lfsr_done); // Design Under Test
initial
begin
reset = 0;
clk = 1;
ce = 0;
#100
ce = 1;
#200 $finish;
end
//Generate Clock
always #10 clk = !clk;
endmodule
But I keep getting these parse errors:
I don't really get it. I'm using Verilogger Pro btw
I think always block terms are separated by or, not a comma.
always #(posedge clk or posedge reset) begin
I have tried connecting a module output to a register, as follows:
module test
(
input rst_n,
input clk,
output reg [7:0] count
);
always #(posedge clk or negedge rst_n) begin
if(!rst_n) begin
count <= 7'h0;
end else begin
if(count == 8) begin
count <= count;
end else begin
count <= count + 1'b1;
end
end
end
endmodule
module test_tb;
reg clk;
reg rst_n;
reg [7:0] counter;
initial begin
clk = 1'b0;
rst_n = 1'b0;
# 10;
rst_n = 1'b1;
end
always begin
#20 clk <= ~clk;
end
test test1 (
.rst_n(rst_n),
.clk(clk),
.count(counter) /* This is the problematic line! */
);
endmodule
I got the error "Illegal output or inout port connection for "port 'count'" in ModelSim. Even though the error matches my code, I do not understand why, fundamentally, I cannot connect a module output to a register.
Why can I not connect a module output to a register in Verilog?
You can only assign a value to a reg within a procedural always block. You can not drive a reg from a module instance. That would be a continuous assisgnment.
Use a wire inside test_tb.