coffee vending machine simulation in verilog with test bench issue - verilog

Question

I have written a verilog code for a simple coffee vending machine with inputs
25ps,50ps,75ps and 1
as
"00","01","10" and "11"
respectively. Coffee cost is 1 rs. If more than 1rs is inserted, the balance will be returned. That balance will be
01, 10, 11
as
25ps, 50ps, 1rs
respectively. I simulate this without test bench. simulation takes double clock pulse for output.(when i put 25 ps 8 times or 8 clock pulses is required for getting output. expected clock pulse is 4). Why this is happens? and also i didn't get output when using the test bench.
please help me to correct the test bench and my programme. Is clock frequency divider is necessary while doing the programme in fpga board to see output? It is working as expected when i programmed into fpga board.Im using Xilinx vivado 2015.2 tool and zynq board.Please help me to solve these issues
//programme
module main(
input clk,
input rst,
input [1:0] money,
output coffee,
output [1:0] balance
);
reg coff;
reg [1:0] bal;
reg [2:0] pr_st;
reg [2:0] nx_st;
parameter [2:0] A=3'b000;
parameter [2:0] B=3'b001;
parameter [2:0] C=3'b010;
parameter [2:0] D=3'b011;
parameter [2:0] E=3'b100;
parameter [2:0] F=3'b101;
parameter [2:0] G=3'b110;
parameter [2:0] H=3'b111;
always # (posedge clk or posedge rst)
begin
if(rst)
pr_st <= A;
else
pr_st <= nx_st;
end
always #(posedge clk)
begin
case(pr_st)
A : if(money == 2'b00) // input money is 25ps
begin
nx_st <= B;
end
else if(money == 2'b01) // input money is 50ps
begin
nx_st <= C;
end
else if(money == 2'b10) // input money is 75ps
begin
nx_st <= D;
end
else if(money == 2'b11)
begin
nx_st <= E;
end
B : if(money == 2'b00)
begin
nx_st <= C;
end
else if(money == 2'b01)
begin
nx_st <= D;
end
else if(money == 2'b10)
begin
nx_st <= E;
end
else if(money == 2'b11)
begin
nx_st <= F;
end
C : if(money == 2'b00)
begin
nx_st <= D;
end
else if(money == 2'b01)
begin
nx_st <= E;
end
else if(money == 2'b10)
begin
nx_st <= F;
end
else if(money == 2'b11)
begin
nx_st <= G;
end
D : if(money == 2'b00)
begin
nx_st <= E;
end
else if(money == 2'b01)
begin
nx_st <= F;
end
else if(money == 2'b10)
begin
nx_st <= G;
end
else if(money == 2'b11)
begin
nx_st <= H;
end
E : nx_st <= A;
F : nx_st <= A;
G : nx_st <= A;
H : nx_st <= A;
default : nx_st <= A;
endcase
end
//output logic
always #( posedge clk or pr_st)
begin
case(pr_st)
A: begin
coff <= 1'b0;
bal <= 2'b00;
end
B: begin
coff <= 1'b0;
bal <= 2'b00;
end
C: begin
coff <= 1'b0;
bal <= 2'b00;
end
D: begin
coff <= 1'b0;
bal <= 2'b00;
end
E: begin
coff <= 1'b1;
bal<= 2'b00;
end
F: begin
coff <= 1'b1;
bal <= 2'b01;
end
G: begin
coff <= 1'b1;
bal <= 2'b10;
end
H: begin
coff <= 1'b1;
bal <= 2'b11;
end
default : begin
off <=1'b0;
bal <= 2'b00;
end
endcase
end
assign coffee = coff;
assign balance = bal;
endmodule
//test bench
module tb_main(
);
reg clk;
reg rst;
reg [1:0] money;
wire coffee;
wire [1:0] balance;
main dut( clk, rst, money, coffee, balance);
always
begin
#200 clock = ~clk;
end
initial
begin
rst = 1'b1;
#100 rst = 1'b0;
money = 2'b00; // putting 25ps four times to get coffee
#400 money = 2'b01; //putting 50ps two times to get coffee
#200 money = 2'b10;// putting 75ps two times to get coffee
#200 money = 2'b11;// putting 1 rs single time to g
#100 money = 2'b01; // putting 1st 25ps and 50ps i n second clock cycle
#100 money = 2'b10;
#200
$finish
end
endmodule

Answer 1

You need to initialize your clock signal to a known value in the testbench. You should speed up the clock because your money input changes faster than the clock:
initial clk = 0;
always begin
#10 clk = ~clk;
end