I am new in Xilinx.
Here's my code,and i want to add clock in it.
Please tell me how to add clock. Thanks
code
module Traffic(
output reg red1,
output reg red2,
output reg red3,
output reg red4,
output reg yel1,
output reg yel2,
output reg yel3,
output reg yel4,
output reg gr1,
output reg gr2,
output reg gr3,
output reg gr4,
input [1:0] c1,
input [1:0] c2
);
always #(c1,c2,red1,red2,red3,red4,yel1,yel2,yel3,yel4,gr1,gr2,gr3,gr4)
begin
case({c1,c2})
4'b0000:begin red1=0;red2=1;red3=1;red4=0; yel1=1;yel2=0;yel3=0;yel4=1; gr1=0;gr2=0;gr3=0;gr4=0; end
4'b0001:begin red1=1;red2=1;red3=1;red4=0; yel1=0;yel2=0;yel3=0;yel4=0; gr1=0;gr2=0;gr3=0;gr4=1; end
4'b0010:begin red1=0;red2=1;red3=1;red4=0; yel1=1;yel2=1;yel3=0;yel4=0; gr1=0;gr2=0;gr3=0;gr4=0; end
4'b0011:begin red1=1;red2=1;red3=1;red4=1; yel1=0;yel2=0;yel3=0;yel4=0; gr1=0;gr2=1;gr3=0;gr4=0; end
4'b0100:begin red1=1;red2=0;red3=0;red4=1; yel1=0;yel2=1;yel3=1;yel4=0; gr1=0;gr2=0;gr3=0;gr4=0; end
4'b0101:begin red1=1;red2=1;red3=0;red4=1; yel1=0;yel2=0;yel3=0;yel4=0; gr1=0;gr2=0;gr3=1;gr4=0; end
4'b0110:begin red1=1;red2=1;red3=0;red4=0; yel1=0;yel2=0;yel3=1;yel4=1; gr1=0;gr2=0;gr3=0;gr4=0; end
4'b0111:begin red1=1;red2=1;red3=1;red4=0; yel1=0;yel2=0;yel3=0;yel4=0; gr1=0;gr2=0;gr3=0;gr4=1; end
endcase
end
endmodule
-------------
Text Fixture
-------------
module tf;
// Inputs
reg [1:0] c1;
reg [1:0] c2;
// Outputs
wire red1;
wire red2;
wire red3;
wire red4;
wire yel1;
wire yel2;
wire yel3;
wire yel4;
wire gr1;
wire gr2;
wire gr3;
wire gr4;
// Instantiate the Unit Under Test (UUT)
Traffic uut (
.red1(red1),
.red2(red2),
.red3(red3),
.red4(red4),
.yel1(yel1),
.yel2(yel2),
.yel3(yel3),
.yel4(yel4),
.gr1(gr1),
.gr2(gr2),
.gr3(gr3),
.gr4(gr4),
.c1(c1),
.c2(c2)
);
initial begin
c1 = 2'b00;c2 = 2'b00;
#100 c1 = 2'b00;c2 = 2'b01;
#100 c1 = 2'b00;c2 = 2'b10;
#100 c1 = 2'b00;c2 = 2'b11;
#100 c1 = 2'b01;c2 = 2'b00;
#100 c1 = 2'b01;c2 = 2'b01;
#100 c1 = 2'b01;c2 = 2'b10;
#100 c1 = 2'b01;c2 = 2'b11;
end
If I understand your question correctly, you would like the outputs of your module to be synchronous to a clock. you need to declare the clock as in input wire, and alter the always block to use the posedge clk. It's also good to add a reset -- you can have a synchronous reset or an asynchronous reset. Here's how such a block would be structured, with an asynchronous reset:
module Traffic(
input wire clk,
input wire resetb, // negative edge asynchronous reset
output reg red1,
output reg red2,
output reg red3,
output reg red4,
output reg yel1,
output reg yel2,
output reg yel3,
output reg yel4,
output reg gr1,
output reg gr2,
output reg gr3,
output reg gr4,
input [1:0] c1,
input [1:0] c2
);
always #(posedge clk or negedge resetb)
begin
if (!resetb) begin
red1 <= 'd0;
// etc....
end else begin
case({c1,c2})
4'b0000:begin
red1<=0;red2<=1;red3<=1;red4<=0;
yel1<=1;yel2<=0;yel3<=0;yel4<=1;
gr1<=0;gr2<=0;gr3<=0;gr4<=0;
end
4'b0001:begin
red1<=1;red2<=1;red3<=1;red4<=0;
yel1<=0;yel2<=0;yel3<=0;yel4<=0;
gr1<=0;gr2<=0;gr3<=0;gr4<=1;
end
// etc...
endcase
end
end
endmodule
Related
I wrote this Verilog code. The inner module is an 8-bit mux, and the top module is used to test the mux. It should display 11110000, but it displayed xxxxxxxx every time. How do I fix this?
module testbench;
reg CLK;
test mytest(CLK);
initial begin
CLK = 1'b0;
#10
CLK = 1'b1;
end
endmodule
module test(CLK);
input CLK;
reg [7:0] in0,in1;
reg sel;
wire [7:0] out;
mux myux(in0,in1,sel,out);
always #(posedge CLK) begin
sel = 1'b0;
in0 = 8'b11110000;
$display("%b",out);
end
endmodule
This is the mux module:
module mux(in0,in1,sel,out);
input sel;
input [7:0] in1,in0;
output [7:0] out;
reg out;
always #(in0,in1,sel) begin
if(sel == 1'b0) begin
out = in0;
end
else begin
out = in1;
end
end
endmodule
The problem is that you did not run your simulation long enough. You only ran it for one clock cycle. Here is one way to change your testbench module to run many clock cycles:
module testbench;
reg CLK;
test mytest(CLK);
initial begin
CLK = 1'b0;
forever #10 CLK =~CLK;
end
initial #1000 $finish;
endmodule
I now see output like this:
xxxxxxxx
11110000
11110000
11110000
11110000
Also, I got a compile error with your code. In your mux module, you should change:
reg out;
to:
reg [7:0] out;
I am building a shift-unit that is capable of arithmetic and logical right shift, and logical left shift depending on the control signals given to it. However, the arithmetic right shift operator output generates output similar to that logical right shift operator, i.e. sign extension does not occur.
Main code
`timescale 1ns / 1ps
module shift_unit(
input [15:0] a,
input [3:0] b,
input clk,
input isLSL,
input isLSR,
input isASR,
output reg [15:0] result
);
wire [15:0] LSL_result, LSR_result, ASR_result;
LSL lsl(a, b, clk, isLSL, LSL_result);
LSR lsr(a, b, clk, isLSR, LSR_result);
ASR asr(a, b, clk, isASR, ASR_result);
always#(posedge clk) begin
case({isLSL, isLSR, isASR})
3'b001: result <= ASR_result;
3'b010: result <= LSR_result;
3'b100: result <= LSL_result;
endcase
end
endmodule
LSL code:
`timescale 1ns / 1ps
module LSL(
input [15:0] a,
input [3:0] b,
input clk,
input isLSL,
output [15:0] out
);
reg [15:0] result;
always#(posedge clk) begin
if(isLSL) result = a << b;
end
assign out = result;
endmodule
LSR code:
`timescale 1ns / 1ps
module LSR(
input [15:0] a,
input [3:0] b,
input clk,
input isLSR,
output [15:0] out
);
reg [15:0] result;
always#(posedge clk) begin
if(isLSR) result = a >> b;
end
assign out = result;
endmodule
ASR code:
`timescale 1ns / 1ps
module ASR(
input [15:0] a,
input [3:0] b,
input clk,
input isASR,
output [15:0] out
);
reg [15:0] result;
always#(posedge clk) begin
if(isASR) result = a >>> b;
end
assign out = result;
endmodule
And finally, the testbench:
`timescale 1ns / 1ps
module shift_unit_test;
reg [15:0] a;
reg [3:0] b;
reg clk;
reg isLSL;
reg isLSR;
reg isASR;
wire [15:0] result;
shift_unit uut (
.a(a),
.b(b),
.clk(clk),
.isLSL(isLSL),
.isLSR(isLSR),
.isASR(isASR),
.result(result)
);
always #5 clk = ~clk;
initial begin
clk = 1'b0;
a = 16'b1100101011001010;
b = 4;
{isLSL, isLSR, isASR} = 3'b100; #100;
{isLSL, isLSR, isASR} = 3'b010; #100;
{isLSL, isLSR, isASR} = 3'b001; #100;
end
endmodule
The above code has been modelled using Xilinx ISE 14.7.
Any help would be greatly appreciated.
You need to be working with signed signals to get sign extension.
module ASR(
input wire signed [15:0] a,
input [3:0] b,
input clk,
input isASR,
output reg signed [15:0] out
);
always#(posedge clk) begin
if(isASR) out = a >>> b;
end
endmodule
My current task is to create a memory driver. The specific issue is that I have a shift register designed to concatenate four 8-bit words into one 32-bit and then send that to the output. The module works when being simulated by itself but it fails to respond when connected to other modules. Here's the code :
The shift register code :
module shiftReg (
data_8,
clk,
valid1,
rstn,
data_32,
valid_fifo,
count,
REGA,
REGB,
REGC,
REGD
);
input wire [7:0] data_8;
input wire valid1;
input wire clk;
input wire rstn;
output reg [31:0] data_32;
output reg valid_fifo;
output reg [3:0] count;
output reg [7:0] REGA;
output reg [7:0] REGB;
output reg [7:0] REGC;
output reg [7:0] REGD;
initial
begin
count <= 4'b0001;
REGA <= 8'b0;
REGB <= 8'b0;
REGC <= 8'b0;
REGD <= 8'b0;
valid_fifo <= 1'b0;
end
always #(posedge valid1)
begin
if(~rstn)
begin
count = 4'b0001;
REGA = 0;
REGB = 0;
REGC = 0;
REGD = 0;
end
else if(valid1 == 1'b1)
begin
case (count)
4'b0001: REGA = data_8;
4'b0010: REGB = data_8;
4'b0100: REGC = data_8;
4'b1000: REGD = data_8;
endcase
valid_fifo = 1'b0;
end
if(count == 4'b1000)
begin
data_32 = {REGD,REGC,REGB,REGA};
valid_fifo = 1'b1;
count = 4'b0001;
end
else
begin
count = count << 1;
end
end
endmodule
The module where I am instantiating it is called altogether.
Here is the code :
module altogether (
input wire BUTTON_AT,
input wire CLK_AT,
input wire RSTN_AT,
output wire MEM_FULL_AT,
output wire EMPTY_AT,
inout wire VALID_IN_AT,
inout wire [7:0] DATA_8_AT,
inout wire VALID1_AT,
inout wire [31:0] DATA_32_AT,
inout wire STOP_AT,
inout wire VALID_FIFO_AT,
inout wire [31:0] DATA_AT,
inout wire WR_AT,
inout wire [6:0] ADDR_AT,
output wire [7:0] REG_A_AT,
output wire [7:0] REG_B_AT,
output wire [7:0] REG_C_AT,
output wire [7:0] REG_D_AT,
output wire [3:0] COUNT_AT
);
shiftReg shift_register (
.data_8(DATA_8_AT),
.clk(CLK_AT),
.valid1(VALID_1_AT),
.rstn(RSTN_AT),
.data_32(DATA_32_AT),
.valid_fifo(VALID_FIFO_AT),
.REGA(REG_A_AT),
.REGB(REG_B_AT),
.REGC(REG_C_AT),
.REGD(REG_D_AT),
.count(COUNT_AT)
);
For some reason, the valid == 1'b1 condition is not executed when I put the shift register along with everything else. I have really run out of ideas, hope someone manages to look at it and give me an insight.
Somewhere during synthesis you probably got warning that you're using VALID_1_AT signal, which has no driver. That's because in altogether module declaration you define VALID1_AT signal (notice _ missing in signal name). That's why valid1 in your shift register is not driven at all.
You should change:
.valid1(VALID_1_AT)
into:
.valid1(VALID1_AT)
to make it works.
This my Verilog code to convert the number x into form x=a0*R+a1 ,e.g 51 = 5*10 +1. My code does not work, it cannot enter the always loop.
`timescale 1ns / 1ps
module poly(
input [15:0] r,
input [15:0] x,
output reg[15:0] a1,
output reg [15:0] a0,
output finish,
input clk,
input reset
);
reg [15:0] sum;
assign finish =(sum > x);
always# (posedge clk )
begin
if(reset)
begin
a0 <=0;
sum <=0;
end
else if (!finish)
begin
a0 <=a0+1;
sum <= sum+r;
end
else
a1<=x-sum;
end
initial begin
$monitor ( "a1=%b,a0=%b,finish=%b,reset=%b",a1,a0,finish,reset);
end
endmodule
testbench
`timescale 1ns / 1ps
module tb_p;
reg [15:0] r;
reg [15:0] x;
wire[15:0] a1;
wire [15:0] a0;
wire finish;
reg clk;
reg reset;
initial clk=0;
always #5 clk=!clk;
poly m1(r,x,a1,a0,finish,clk,reset);
initial begin
r<=10;
x <=17;
#1 reset<=1;
#2 reset<=0;
end
endmodule
Since your reset signal is synchronous to the clock, you need to extend it so that it is high for at least one posedge of the clock:
initial begin
r<=10;
x <=17;
#1 reset<=1;
#20 reset<=0;
#500 $finish;
end
Note that I added $finish just so my simulation would end.
I have the following verilog code. Idea is to store value of counter at the time of reset. However, I am not sure if it would be synthesizable(memories need synchronous reset). I get DRC violatins and the memory, bufreadaddr, bufreadval are all optimized out. What are some other ways to write this?
module counter (clk,reset, d_out,laststoredvalue, bufreadaddr, bufreadval, resetcount) ;
input clk ,reset ;
input [5:0] resetcount;
output [15:0] d_out;
output [15:0] laststoredvalue;
input [5:0] bufreadaddr;
output [15:0] bufreadval;
reg [15:0] bufreadval;
reg [15:0] laststoredvalue;
reg [15:0] d_out;
reg [15:0] d_out_mem[63:0];
always #(negedge reset or posedge clk) begin
if (reset == 0) begin
d_out <= 16'h0000;
d_out_mem[resetcount] <= d_out;
laststoredvalue <= d_out;
end else begin
d_out <= d_out + 1'b1;
end
end
always #(bufreadaddr)
bufreadval = d_out_mem[bufreadaddr];
integer count;
initial begin
count = 0;
end
always #(posedge clk ) begin
count = count + 1;
//$display(count);
end
endmodule
hi i have made a small change for your code; added a temporary variable to store the output in a register it will store previous value on reset;
module counter (clk,reset, d_out,laststoredvalue, bufreadaddr, bufreadval, resetcount) ;
input clk ,reset ;
input [5:0] resetcount;
output [15:0] d_out;
output [15:0] laststoredvalue;
input [5:0] bufreadaddr;
output [15:0] bufreadval;
reg [15:0] bufreadval;
reg [15:0] laststoredvalue;
reg [15:0] temp;
reg [15:0] d_out;
reg [15:0] d_out_mem[63:0];
always #(negedge reset or posedge clk) begin
if (reset == 0) begin
d_out_mem[resetcount] = d_out;
laststoredvalue = temp;
d_out = #10 16'h0000;
end
else begin
d_out = d_out + 1'b1;
temp = d_out;
end
end
always #(bufreadaddr)
bufreadval = d_out_mem[bufreadaddr];
endmodule
remaining code is same as it is.