I have a conditional 2-bit variable coming in. Based off its value, the current value is either incremented or decremented. By that, I mean:
module verilog_block(clk, cond, incr, curr_val)
input clk;
input [1:0] cond;
input [5:0] incr;
output reg [5:0] curr_val;
always # posedge(clk)
begin
curr_val <= curr_val + (!cond[1] - cond[1]) * incr * cond[0];
end
endmodule
Sorry if I made any mistakes, I haven't checked this specific code, as I am just trying to illustrate my question. If cond[0]==0, I don't want curr_val to change (irrespective of cond[1]). If cond[1]==1, I want curr_val to reduce by incr, and if cond[1]==0, I want curr_val to increment by incr.
I think this works, theoretically, but my goal is to expand this into a much larger code. Therefore, it needs to be optimized. I know that the * operator can be slow and require a lot of resources, but I am not sure if that applies to the case of multiplication with only one bit.
If you can spot a way to make this code optimized for area, please let me know. Thanks a lot.
Any good synthesis tool will optimize multiplication where it can, especially when it involves multiplication by zero or any power of 2. But you've created a very hard to read operation. Why not write it the way you said it:
always # posedge(clk)
begin
if (cond[0]==1)
curr_val <= curr_val + (cond[1]==1) ? -incr : incr;
end
Apology the title does not explain the question very well, I'll explain it in detail down below.
I'm new to verilog and got painfully stuck with my first lab assignment. One task is to make a 4*4 carry save multiplier, which is made of two types of multipliers, which are in turn made of full adders and AND gates, full adders are made of half adders. I built from the simplest half adders all the way up to the carry save multiplier.
two types of multipliers: http://i129.photobucket.com/albums/p205/Jack_Tianyu_Yang/Capture1_zpsf34b724c.png
hand-drawing of the carry save multiplier
http://i129.photobucket.com/albums/p205/Jack_Tianyu_Yang/photo_zps905f2c13.jpg
The code for the carry save multiplier is here. I instantiated the two types of multipliers and use a lot of internal wires for connections. (I admit it's pretty naive but this is the best i can do for the time being, I'll keep practicing and get better at it.) My QUESTION is this: refer to the "hand-drawing" ,the most left module on the top row, you can see there are two ports---q0_out and q1_out, that are outputs of this multiplier module BUT not part of the outputs in the main output list. Actually, q0_out,q1_out,q2_out,q3_out and m0_out,m1_out,m2_out,m3_out are all not in the output list. They are actually the same value of q0 to q3 and m0 to m3,respectively. (This can be verified by the first image)
When I synthesized the code I pasted below, Xilinx ISE gave me a bunch of same warnings saying for example :"Assignment to q3_out ignored, since the identifier is never used".
When I ask the TA, he said I should "treat the 4*4 carry save multiplier as a black box and the only inputs are m3m2m1m0, q3q2q1q0 and the only output is p7p6p5p4p3p2p1. Outputs like q3_out are 'internal' and should not be presented in the final output list". I don't how to deal with this situation. As you can see, I simply assign q3 to q3_out because q3_out is the same value propagated all the way from q3.
Please feel free to comment on my codes (what to improve, what's a bad coding style) and ask me for more elaboration of the question, also, if possible, please please share some ideas of how to solve this problem. Thank you all in advance.
`timescale 1ns / 1ps
module multiplier44_OMG(
input m0,m1,m2,m3,q0,q1,q2,q3,
output p0,p1,p2,p3,p4,p5,p6,p7
);
wire w1,w2,w3,w4,w5,w6,w7,w8,w9,w10,w11,w12,w13,w14,w15,w16,w17,w18,w19,w20;
wire w21,w22,w23,w24,w25,w26,w27,w28,w29,w30,w31,w32,w33,w34,w35,w36,w37; //Internal wires
wire cin0,cin1,cin2,mk1_mul2_3; //These inputs are feeding into the carry save multiplier and are all zeroes.
wire q0_out,q1_out,q2_out,q3_out,m0_out,m1_out,m2_out,m3_out;
assign cin0=1'b0;
assign cin1=1'b0;
assign cin2=1'b0;
assign mk1_mul2_3=1'b0;// Inputs are assigned to zero.
assign q0_out=q0;
assign q1_out=q1;
assign q2_out=q2;
assign q3_out=q3;
assign m0_out=m0;
assign m1_out=m1;
assign m2_out=m2;
assign m3_out=m3;//THIS IS THE PART I DON'T KNOW HOW TO DEAL WITH
and (p0,m0,q0);
multiplier2 mul2_0(m1,m0,q0,q1,cin0,w1,w2,w3,w4,p1);
multiplier2 mul2_1(m2,m1,w1,w2,w3,w5,w6,w7,w8,w9);
multiplier2 mul2_2(m3,m2,w5,w6,w7,w10,w11,w12,w13,w14);
multiplier2 mul2_3(mk1_mul2_3,m3,w10,w11,w12,q0_out,q1_out,w15,w16,w17);
multiplier mul_0(w9,w4,q2,cin1,w18,w19,w20,p2);
multiplier mul_1(w14,w8,w18,w19,w21,w22,w23,w24);
multiplier mul_2(w17,w13,w21,w22,w25,w26,w27,w28);
multiplier mul_3(w15,w16,w25,w26,q2_out,w29,w30,w31);
multiplier mul_4(w24,w20,q3,cin2,w32,w33,m0_out,p3);
multiplier mul_5(w28,w23,w32,w33,w34,w35,m1_out,p4);
multiplier mul_6(w31,w27,w34,w35,w36,w37,m2_out,p5);
multiplier mul_7(w29,w30,w36,w37,q3_out,p7,m3_out,p6);
endmodule
It's does not feel any good staring at the code alone in the lab on a friday night.(Plus it's Spring festival.) I know my question is quite elementary, but even though I need help, GREAT help from the GREAT netizens.
A warning is just a warning, it's not an error. If you have a signal that is generated that has no load, then the synthesizer warns you, but there's nothing really there to 'fix'.
Also, since q3_out is output from mul_7, you shouldn't be driving it with a separate assign statement. Each wire should only have one driver.
I just want to use some if else statement in verilog.
So I have to use always block.
integer count,index;
reg a=0;
always#(a) begin
a=1;
for(count=0;count<7;count=count+1) begin
index=4*count;
if((significand[index]==1'b0)&&(significand[index+1]==1'b0)&&
(significand[index+2]==1'b0) &&(significand[index+3]==1'b0))
lzero=lzero+1;
end
end
This code does make some sense now. I was able to get the correct simulation result, but I failed to get the correct synthesis on the board. Please help
This is a very typical problem with people who know how to program in C or C++ but forget that Verilog and VHDL are not the same as those.
EVERY signal line of Verilog code inside the ALWAYS block are 'executed' at the same time. The same goes with the combinatorial logic outside of the ALWAYS block.
In your code, both the
assign a=1'b1;
assign a=1'b0;
Will happen at the same time, no matter what.
The only way to change that is to put the last line inside your always block,after the end statement of the for loop.
One page that will give you some help on understanding the difference between C and Verilog is the page:EE-Times: The C Programmers Guide to Verilog
Neither assign 1'b1; nor assign 1'b0; are valid assignments. If you want to constantly drive some net with 1'b1, then you have to write something like assign myvar = 1'b1;.
Also, if your intent was to actually assign to a, then always block doesn't make sense since a is the only thing in its sensitivity list meaning that that block must be executed whenever a changes its value. Since a will essentially never change its value, that block should never be executed.
It is hard to help you out unless you provide a minimal working example demonstrating your problem. The only thing that I can recommend is to use ternary operator in assign right hand side statement. That way you can model a behavioural logic without using always block. For example:
assign a = (b == 1'b1 ? c : 1'b0);
Hope it helps.
UPDATE:
Your second code example is neither complete nor legal as well. You cannot have two combinatorial assignments for the same net.
However, a sensitivity list in always block is now a star, which is Verilog 2001 notation to include all right hand side operands into a sensitivity list automatically. In your case, the block will get executed every time significand or lzero changes.
I'm a bit confused about what is considered an input when you use the wildcard #* in an always block sensitivity list. For instance, in the following example which signals are interpreted as inputs that cause the always block to be reevaluated? From what I understand clk and reset aren't included because they dont appear on the right hand side of any procedural statement in the always block. a and b are included because they both appear on the right hand side of procedural statements in the always block. But where I'm really confused about is en and mux. Because they are used as test conditions in the if and case statements are they considered inputs? Is the always block reevaluated each time en and mux change value? I'm pretty much a noob, and in the 3 Verilog books I have I haven't found a satisfactory explanation. I've always found the explanations here to be really helpful. Thanks
module example
(
input wire clk, reset, en, a, b,
input wire [1:0] mux,
output reg x,y, z
);
always #*
begin
x = a & b;
if (en)
y= a | b;
case(mux)
2'b00: z = 0;
2'b01: z = 1;
2'b10: z = 1;
2'b11: z = 0;
endcase
end
endmodule
Any signal that is read inside a block, and so may cause the result of a block to change if it's value changes, will be included by #*. Any change on a read signal used must cause the block to be re-evaluated, as it could cause the outputs of the block to change. As I'm sure you know, if you hadn't used #* you'd be listing those signals out by hand.
In the case of the code you've provided it's any signal that is:
Evaluated on the right hand side of an assignment (a and b)
Evaluated as part of a conditional (en and mux)
...but it's any signal that would be evaluated for any reason. (I can't think of any other reasons right now, but maybe someone else can)
clk and reset aren't on the sensitivity list because they aren't used. Simple as that. There's nothing special about them; they're signals like any other.
In your example, the following signals are included in the implicit sensitivity list:
a
b
en
mux
clk and reset are not part of the sensitivity list.
This is described completely in the IEEE Std for Verilog (1800-2009, for example). The IEEE spec is the best source of detailed information on Verilog. The documentation for your simulator may also describe how #* works.
The simplest answer depends on if you are writing RTL, or a testbench. If you are writing RTL then you should try to forget about the concept of Sensitivity lists, as they don't really exist. There is no logic that only updates when an item on the list is triggered. All sensitivity lists can do in RTL is cause your simulation and actual circuit to differ, they don't do anything good.
So, always use "always #*" or better yet "always_comb" and forget about the concept of sensitivity lists. If the item in the code is evaluated it will trigger the process. Simple as that. It an item is in an if/else, a case, assigned to a variable, or anything else, it will be "evaluated" and thus cause the process to be triggered.
But, just remember, in digital circuits, there is no sensitivity list.