In a Verilog module, what is the proper terminology for arguments?
What does a variable default to when it's not defined?
A module in Verilog represents hierarchy that is only used for grouping objects by name and replicating those objects. When you run a simulation or synthesize to hardware, that hierarchy gets flattened. Ports of a module join two signal names together, and after flattening, there is only one signal with multiple names. So modules are structurally connected through ports.
The term argument is terminology from software that usually represents a object that gets copied or referenced when you procedurally call a routine like a function or task.
For your second question, if you refer to a variable without defining it, that is usually a compiler error. There is one exception to that for lazy engineers. If you refer to a undefined variable in a port connection, that variable is implicitly declared as a 1-bit wire. If nothing drives that wire, it has the default value 'z which is treated the same as 'x in any expression.
This feature was originally intended for automatically generated gate-level net-lists where every signal is a 1-bit wire, but causes many problems for RTL descriptions. We strongly recommend that use use the compiler directive `default_nettype none to prevent careless typos.
They are called ports . A Verilog module cannot be called like a function, as it is meant to represent a hardware module with input , output , bi-directional pins etc , so it can only be instanced. These instances can be connected to each other again via their ports. These ports bring in and take out data/value/signals into and out of the modules. Hence ports have direction associated with them. Unlike an arguments in a function which only passes on the value when the function is called , once a connection is made to a port ( via a wire/reg (register) / ...) any change to the connected variable is transferred to the module via the port automatically.
link to a module- port explanation.
http://www.asic-world.com/verilog/syntax2.html
Verilog does have functions and tasks which take arguments.
http://www.asic-world.com/verilog/task_func1.html
Uninitialized variables take on unknown value represented by "x" .
There are a few nuances to it
unconnected wire , tri will be tri-state represented by "z"
any 4 state logic - reg , integer , time will default to "x"
real type to 0 .
Related
Hello I’m new to Verilog and I’ve been confused over this. In some examples the inputs and outputs are declared as wires or regs and on others they are just listed like this:
Module(input a, b, output c)
What is the default data type given to these values?
The default data type for a port in any direction is an unsigned 4-state scalar (1 binary digit). In Verilog, input and inout ports must be and default to the net type wire. output ports also default to wire but can also be specified as a variable reg. (SystemVerilog relaxes some of these rules by allowing input ports to also be declared as variables).
Now that you know what the implicit defaults are, please be a good engineer and never rely on them—be explicit.
Say I have a Verilog module that's parameterizable like the below example:
// Crunches numbers using lots of parallel cores
module number_cruncher
#(parameter NUMBER_OF_PARALLEL_CORES = 4)
(input clock, ..., input [31:0] data, ... etc);
// Math happens here
endmodule
Using Verilog 1364-2005, I want to write a testbench that runs tests on this module with many different values NUMBER_OF_PARALLEL_CORES.
One option that I know will work is to use a generate block to create a bunch of different number_crunchers with different values for NUMBER_OF_PARALLEL_CORES. This isn't very flexible, though - the values need to be chosen at compile time.
Of course, I could also explicitly instantiate a lot of different modules, but that is time consuming and won't work for the sort of "fuzz" testing I want to do.
My questions:
Is there a way to do this by using a plusarg passed in from the command line using $value$plusargs? (I strongly suspect the answer is 'no' for Verilog 1364-2005).
Is there another way to "fuzz" module parameterizations in a testbench, or is using a generate block the only way?
Since $value$plusargs is evaluated at runtime, it can not be used to set parameter values, which must be done at compile-time.
However, if you use generate to instantiate multiple instances of the design with different parameter settings, you might be able to use $value$plusargs to selectively activate or enable one instance at a time. For example, in the testbench, you could use the runtime argument to only drive the inputs of a specific instance.
Just came across this issue and after doing a little reading, it seems that this isn't allowed in System Verilog, but it seems a little obtuse and I wonder if I am missing some easy workaround.
I have an interface that was defined as if_datapath. The interface does have some modports called sink, source and monitor and I am able to use the interface on modules without issue.
However, if I define a the interface within a module as nither sink, source or monitor:
if_datapath #(.EW(5),.DW(256),.SW(64),.QW(32)) dp_buf_0 (.clk(clk), .reset(reset));
I can use this to route my interface through hierarchy. But if instead of using it for routing, I write the following:
always # (posedge clk)
begin
dp_buf_0 <= dp_in; // Where dp_in is the same kind of
//interface as dp_buf_0
end
I get an error that says:
An instance name is not a legal lvalue [7.1(IEEE)].
So if I want to register my entire interface, I need to break out the individual parts? Tell me I am missing something here.
Interfaces and modules are just containers that create hierarchical name spaces for the items inside those containers. They also give you ways of making connections the signals within those containers. Interfaces give you a few more ways of making connections, and a modport is a construct that limits access to things inside the interface.
Interfaces are not data types, and interface instances are not variables, so you cannot perform the same kinds of operations that you would on a variable.
But you can define a struct as a data type, and then create a wire or variable using that data type. Then you can perform all the same operations that you could on a wire or variable.
I am a beginner in circuit synthesis, and I came across the word net a lot, but I am never able to find its standard definition. It seems to me that it refers to any kind of "black box" where it receives inputs and produce outputs. So it can be a sub circuit inside a big circuit and it can be an array of gates. Is my understanding correct?
No, your understanding is not correct.
Verilog
In Verilog, net has a precise definition:
IEEE 1800-2012 states:
6.5 Nets and variables
There are two main groups of data objects: variables and nets. These two groups differ in the way in which they
are assigned and hold values.
A net can be written by one or more
continuous assignments, by primitive outputs, or through module ports.
The resultant value of multiple drivers is determined by the
resolution function of the net type. A net cannot be procedurally
assigned.
A net can be one of many types, for example: wire, supply0, wand, but by far the most common type is wire.
IEEE 1800-2012 goes on to say:
Variables can be written by one or more procedural statements,
including procedural continuous assignments. The last write determines
the value. Alternatively, variables can be written by one continuous
assignment or one port.
The main difference between the behaviour of a variable and a net is their behaviour when assigned to from more than one place, as highlighted by the bold text in the two quotes:
For a net, if you assign to it from more than one place, its resulting value is determined by a resolution function, which for the built-in net types (wire etc). The behaviour of the resolution function depends on the net type and that is the difference between the net types. So, for example, with a wire, if both 1'b0 and 1'b1 are assigned to it, the resulting value will be 1'bx (unknown) if both assignments assign values with the same strength. The resolution function is intended to model real electronics. (There is also the added complication of user-defined net types and drive strengths, but let's leave those out for this discussion.)
For a variable, if you assign to it from more than one place, its resulting value is determined by whatever value is written last (just like a normal software variable). So, for example, if a 1'b0 is assigned and then a 1'b1 is assigned, the resulting value will be 1'b1 because that value was assigned last. There is no resolution function involved nor any concept of drive strength.
Both nets and variables are used to model combinational logic and sequential logic. There are rules for when you can use a net and when you can use a variable and the choice of which to use is governed by those rules (given in the quotes above). These were strict in verilog, but have been relaxed in System-Verilog to such an extent that, if you are not designing using tri-state logic, you don't need nets in System-Verilog.
VHDL has exactly the same distinction. The VHDL equivalent of a Verilog net is a signal; the VHDL equivalent of a Verilog variable is a variable. The rules about which to use where in VHDL are different, however, and more strict (no surprise there).
Electronics
In electronics a net means a piece of metal through which current flows. In other words, a net is the connection between one place and another. Physically, it could be a PCB track, a cable, a bond wire or a metal connection on an IC. Generally, in digital electronics, it is most like to be a metal connection on an IC.
Synthesis
So, to answer your question, if someone uses the term "net" when talking about the output of a logic synthesiser (the gate-level netlist), they almost certainly mean the second idea: the construct in whatever format that gate-level netlist uses that models the connection between one gate and another. As it is common for synthesisers to output their gate-level netlist as Verilog, those connections between gates are probably modeled using Verilog nets anyway (probably wires).
Please help to understand the following syntax of verilog port definition.
module same_port (.a(i), .b(i));
// Name ’i’ is declared inside themodule as a inout port.
// Names ’a’ and ’b’ are
// defined for port connections.
Is this connection legal?
Yes, this is legal. It looks like you took this example straight from section 23.2.2.1 of the standard (Non-ANSI style port declarations). As it says there you have two ports a and b which are both connected to internal net i. When you instantiate this module you can use named port connections to connect two different things to i:
same_port inst(.a(connection1), .b(connection2));
In the above instantiation, both connection1 and connection2 will be connected to inst.i.
Even though this is legal, I would advise against using it unless you have a good reason to. This is not very commonly used syntax and could cause confusion for someone else looking at your code. The only place I have seen this is in a verilog netlist automatically generated from an schematic.