I'm trying to make a counter on verilog using ise xilinx 14.7, webpack version.
Actually, I copied a counter from the book "Digital Design using digilent FPGA Boards" by R. Haskell and D. Hanna in order to understand it and make some modifications.
While syntaxis is all good, when I try to Synthetize the top module, it says unexpected token and illegal redeclaration about variables I'm calling from one of the modules, just like this picture shows. I'm new to verilog, please, if you could tell me what I'm doing wrong, I'd be very thankful.
picture
Your problem is the instantiation of the clockdiv module on line 16. The proper syntax for instantiating a module is like so:
module_name instance_name(port_connections);
Where module_name is the name of the module you want to instantiate, instance_name is the name given to this particular instance of the module, and port_connections are the connections of the input, output and inouts of the module, in either .name(connection), or ordered list style. So, I think you meant to say:
clockdiv U1( .mclk(mclk),
.clr(clr),
.clk190(clk190),
.clk48(clk48));
Related
I'm trying to build a Verilog file that imports global definitions from a defines file so I can keep track of all my FPGA endpoints in one place. In the my_defines file I have a list of variables like so:
`define PipeA 8'hA1
I import this file into the main file top_module using `include "my_defines.v"
When I instantiate the variable inside my top_module file, I noticed that you have to use `PipeA as the variable name instead of PipeA. If I've already imported this, why do I need the `?
`include is a verilog syntax which directs a compiler to include contents of other files in compilation. It is very similar to #include in C.
`define defines a named text replacement (macro), similar to the #define in C.
So, `define PipeA 8'hA1 defines the macro named PipeA with 8'h1 as a context. To use it in a program you need to follow verilog rules and to use the '`' syntax, as here: `PipeA.
An example
assign myVar[7:0] = `PipeA;
The pre-processor will replace `PipeA with the text form its definition:
assign myVar[7:0] = 8'h1;
The above result will be parsed by verilog.
Macro definitions are concidered global. The definition interpretation happens before any verilog analysis and is ortogonal to the scoping rules. So, no matter whre you define the macro, in a scope or outside a scope, it will still be defined everywhere within a compilation unit.
Also, standard Verilog does not have any concept of import. System verilog does, but it has nothing to do with the above.
There's a big difference between `include and import. import is something only SystemVerilog allows. The use of `define is text substitution in a pre-processing step without understanding any Verilog syntax. `PipeA invokes a text substitution macro, it is not a variable name. There is no global namespace as far as Verilog is concerned.
SystemVerilog has a package you can define which is a namespace that can be imported into a module (or another package).
I have a top level file where I have an instance of an interface. This is the code in my toplevel file
LC3_io top_io; // LC3_io is the interface which is defined seperately in my interfaces file.
LC3_test test(top_io); // Passing the interface to my testbench
test is the instance of my LC3_test(Testbench).
Now, after passing this interface to my Testbench . I have a separate testbench file where my first line of code is :
program automatic LC3_test(LC3_io.TB top_io);
I have written some other code in the testbench.
The problem when I am trying to simulate the testbench is :
**Fatal: (vsim-3695) DUT_Testing.sv(0) : The interface port 'top_io' must be passed an actual interface.
FATAL ERROR while loading design.
I do not understand where the problem could lie. I am compiling all the necessary files using vlog and trying to run/ simulate my testbench using vsim. I have tried removing program and using a module instead for the testbench but the problem persists. Is there anything I am missing here ? Thanks
It seems to me that the types don't match. You're expecting an argument of type LC3_io.TB for your program block, but you're passing in an interface of type LC3_io. Try changing your code to this:
// pass the TB modport from 'top_io'
LC3_test test(top_io.TB);
I have an erlang program, compiled with rebar, after the new debian release, it won't compile anymore, complaining about this:
-import(erl_scan).
-import(erl_parse).
-import(io_lib).
saying:
bad import declaration
I don't know erlang, I am just trying to compile this thing.
Apparently something bad happened to -import recently http://erlang.org/pipermail/erlang-questions/2013-March/072932.html
Is there an easy way to fix this?
Well, -import(). is working but it does NOT do what you are expecting it to do. It does NOT "import" the module into your module, nor does it go out, find the module and get all the exported functions and allow you to use them without the module name. You use -import like this:
-import(lists, [map/2,foldl/3,foldr/3]).
Then you can call the explicitly imported functions without module name and the compiler syntactically transforms the call by adding the module name. So the compiler will transform:
map(MyFun, List) ===> lists:map(MyFun, List)
Note that this is ALL it does. There are no checks for whether the module exists or if the function is exported, it is a pure naive syntactic transformation. All it gives you is slightly shorter code. For this reason it is seldom used most people advise not to use it.
Note also that the unit of code for all operations is the module so the compiler does not do any inter-module checking or optimisation at all. Everything between modules like checking a modules existence or which functions it exports is done at run-time when you call a function in the other module.
No, there is no easy way to fix this. The source code has to be updated, and every reference to imported functions prefixed with the module in question. For example, every call to format should be replaced with io_lib:format, though you'd have to know which function was imported from which module.
You could start by removing the -import directives. The compilation should then fail, complaining about undefined functions. That is where you need to provide the correct module name. Look at the documentation pages for io_lib, erl_scan and erl_parse to see which functions are in which module.
Your problem is that you were using the experimental -import(Mod) directive which is part of parameterized modules. These are gone in R16B and onwards.
I often advise against using import. It hurts quick searches and unique naming of foreign calls. Get an editor which can quickly expand names.
Start by looking at what is stored in the location $ERL_LIBS, typically this points to /usr/lib/erlang/lib.
I am new to the linux kernel. I have searched a little bit of EXPORT_SYMBOL but I still get a little confused. I know it's used to export a variable or function defined in one module to another module. Does that mean by using that, we do not need to include any header file that declares that variable or function? Or are they both needed? If both needed , why do we need to have EXPORT_SYMBOL? Thanks,
Header files are for the compiler. EXPORT_SYMBOL is for the module loader. This allows for proper separation of module code from kernel code.
I used coregen to develop a divider core. Here are the steps I tried to use that divider in my design (not sure if its quite correct):
1) copied wrapper (core_name.v), .ngc file, and .veo file into main design folder
2) instantiate the core in my main verilog module using the veo template: core_name u1(.a(a_p), .b(b_p), .c(c_p), .d(d_p); whenever I need the divide function in my main verilog module
3) `include "core_name.v"
When I do a syntax check I get:
"core_name.v" line 1 expecting 'endmodule', found 'module'
Please advise on the steps needed to instantiate the core in my ISE design and synthesize it.
Thank you.
I'm going to assume that core_name.v is a full module definition, and that you've put the ``include "core_name.v"within another module definition (ie, betweenmoduleandendmodulestatements. (I'm thinking this because the verilog parser will want to see anendmodulesometime after amodule, but instead is seeing anothermoduleincore_name.v`).
Try putting the ``include` outside your module definition, eg
`include "core_name.v"
module toplevel_module ( );
core_name U0 ( .. );
endmodule
instead of what I assume you have:
module toplevel_module ( );
`include "core_name.v"
core_name U0 ( .. );
endmodule