LKM Makefile, extract source files from source directories - linux

Question

I have the following project structure for a simple kernel module and I want to be able to build this by extracting the source files from the provided source directories in the Makefile.
Makefile
src/
main.c
sub_src/
sub_src.c
sub_src.h
I will describe my issue soon but I will first provide the code.
main.c :
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include "sub_src/sub_src.h"
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Unknown");
MODULE_DESCRIPTION("A Simple Hello World module");
static int __init hello_init(void)
{
printk(KERN_INFO "Hello world!\n");
sub_src_printk("sub_src.c\n");
return 0;
}
static void __exit hello_cleanup(void)
{
printk(KERN_INFO "Cleaning up module.\n");
}
module_init(hello_init);
module_exit(hello_cleanup);
sub_src.h :
#ifndef __SUB_SRC_H___
#define __SUB_SRC_H___
#include <linux/kernel.h> // included for KERN_INFO
void sub_src_printk( const char* );
#endif /* __SUB_SRC_H___ */
sub_src.c :
#include "sub_src.h"
void sub_src_printk( const char* msg )
{
printk(KERN_INFO "%s", msg);
}
Makefile :
MODULE_NAME ?= test_module
TEST ?= 0
INCLUDE_DIRS = -I$(src)/src/sub_src
ccflags-y := $(INCLUDE_DIRS)
ifeq ($(TEST), 1)
SRC_DIRS := \
src \
src/sub_src
SRCS := $(foreach src_dir,$(SRC_DIRS),$(wildcard $(src_dir)/*.c))
else
SRCS := \
src/main.c \
src/sub_src/sub_src.c
endif
#extract required object files
OBJ_SRCS := $(SRCS:.c=.o)
#setup kbuild
obj-m += $(MODULE_NAME).o
$(MODULE_NAME)-y := $(OBJ_SRCS)
$(MAKE) = make
KERNEL_DIR := /lib/modules/$(shell uname -r)/build
all:
#echo ""
#echo "------- Building the LKM ($(MODULE_NAME).ko) -------"
#echo "INCLUDE_DIRS = $(INCLUDE_DIRS)"
#echo "SRCS = $(SRCS)"
#echo "OBJS_SRCS = $(OBJ_SRCS)"
#echo "ccflags-y = $(ccflags-y)"
#echo "obj-m = $(obj-m)"
#echo "test_module-y = $(test_module-y)"
#echo "-----------------------------------------------------"
#echo ""
$(MAKE) -C $(KERNEL_DIR) M=$(PWD) modules
clean:
$(MAKE) -C $(KERNEL_DIR) M=$(PWD) clean
The idea is that I should be able to build this module by providing only the source directories in the Makefile by calling make as:
make all TEST=1
But I have the option (for now) to provide the path to the source files by calling make as following:
make all TEST=0
These two calls should ideally provide the same result i.e a functional kernel module ready to be inserted (via sudo insmod ...). This is however not the case. (make all TEST=0 works as intended while make all TEST=1 does not)
make all TEST=0 gives the following output: (make clean has been called before this command)
------- Building the LKM (test_module.ko) -------
INCLUDE_DIRS = -I/src/sub_src
SRCS = src/main.c src/sub_src/sub_src.c
OBJS_SRCS = src/main.o src/sub_src/sub_src.o
ccflags-y = -I/src/sub_src
obj-m = test_module.o
test_module-y = src/main.o src/sub_src/sub_src.o
-----------------------------------------------------
make -C /lib/modules/3.19.0-59-generic/build M=/home/henrik/Desktop/test_lkm_dev/new_test modules
make[1]: Entering directory `/usr/src/linux-headers-3.19.0-59-generic'
CC [M] /home/henrik/Desktop/test_lkm_dev/new_test/src/main.o
CC [M] /home/henrik/Desktop/test_lkm_dev/new_test/src/sub_src/sub_src.o
LD [M] /home/henrik/Desktop/test_lkm_dev/new_test/test_module.o
Building modules, stage 2.
MODPOST 1 modules
CC /home/henrik/Desktop/test_lkm_dev/new_test/test_module.mod.o
LD [M] /home/henrik/Desktop/test_lkm_dev/new_test/test_module.ko
make[1]: Leaving directory `/usr/src/linux-headers-3.19.0-59-generic'
make all TEST=1 gives the following output: (make clean has been called before this command)
------- Building the LKM (test_module.ko) -------
INCLUDE_DIRS = -I/src/sub_src
SRCS = src/main.c src/sub_src/sub_src.c
OBJS_SRCS = src/main.o src/sub_src/sub_src.o
ccflags-y = -I/src/sub_src
obj-m = test_module.o
test_module-y = src/main.o src/sub_src/sub_src.o
-----------------------------------------------------
make -C /lib/modules/3.19.0-59-generic/build M=/home/henrik/Desktop/test_lkm_dev/new_test modules
make[1]: Entering directory `/usr/src/linux-headers-3.19.0-59-generic'
make[2]: *** No rule to make target `/home/henrik/Desktop/test_lkm_dev/new_test/test_module.c', needed by `/home/henrik/Desktop/test_lkm_dev/new_test/test_module.o'. Stop.
make[1]: *** [_module_/home/henrik/Desktop/test_lkm_dev/new_test] Error 2
make[1]: Leaving directory `/usr/src/linux-headers-3.19.0-59-generic'
make: *** [all] Error 2
The debugging info shows (as far I can see) that the variables in the Makefile contains the same values with the different approaches.
But the second alternative (TEST=1) somehow have the impression that there should be a source file called test_module.c which isn't the case.
Do someone/anyone have an idea why this happens and how I can solve it? (I have been pulling my hair out for the last two hours..)
Solution (The Makefile):
MODULE_NAME ?= test_module
TEST ?= 0
INCLUDE_DIRS = -I$(src)/src/sub_src
ccflags-y := $(INCLUDE_DIRS)
ifeq ($(TEST), 1)
# Paths to source directories
SRC_DIRS := \
src \
src/sub_src
SRCS := $(foreach src_dir,$(SRC_DIRS),$(wildcard $(src)/$(src_dir)/*.c))
SRCS := $(SRCS:$(src)/%=%)
else
SRCS := \
src/main.c \
src/sub_src/sub_src.c
endif
# extract required object files
OBJ_SRCS := $(SRCS:.c=.o)
# setup kbuild
obj-m := $(MODULE_NAME).o
$(MODULE_NAME)-y := $(OBJ_SRCS)
$(MAKE) = make
KERNEL_DIR := /lib/modules/$(shell uname -r)/build
all:
#echo ""
#echo "------- Building the LKM ($(MODULE_NAME).ko) -------"
ifeq ($(TEST), 1)
#echo "Compiling with TEST = 1"
else
#echo "Compiling with TEST = 0"
endif
#echo ""
$(MAKE) -C $(KERNEL_DIR) M=$(PWD) modules
clean:
$(MAKE) -C $(KERNEL_DIR) M=$(PWD) clean
Many thanks!
Henrik