Here is the code I have written:
reg number;
always #(posedge clk)
begin
case(SW[3:1])
000: number = 32h'A65D;
001: number = 32h'BAB9;
010: number = 32h'9430;
011: number = 32h'8BEB;
100: number = 32h'7CB8;
101: number = 32h'62F1;
110: number = 32h'6EF9;
111: number = 32h'5D5C;
default: number = 32h'0000;
endcase
end
I keep getting an error in quartus for every line saying:
"Error (10170): Verilog HDL syntax error at test.v(181) near text "h";
expecting ";""
How I can resolve this error?
You need to specify a bit width for number; it is currently 1-bit wide and you likely want 32 bits. You need to add a size and a base radix (3'b) to each of the case items:
reg [31:0] number;
always #(posedge clk)
begin
case(SW[3:1])
3'b000: number <= 32'hA65D;
3'b001: number <= 32'hBAB9;
3'b010: number <= 32'h9430;
3'b011: number <= 32'h8BEB;
3'b100: number <= 32'h7CB8;
3'b101: number <= 32'h62F1;
3'b110: number <= 32'h6EF9;
3'b111: number <= 32'h5D5C;
default: number <= 32'h0000;
endcase
end
You should use nonblocking assignments (<=) for sequential logic.
UPDATE: ...and of course after seeing Eugenio Lyatte's answer, fix the 'h syntax error, too.
You need change 32h'A65D for 32'hA65D. This will be resolve your error.
reg [31:0]number
always #(posedge clk)
begin
case(SW[3:1])
3'b000: number <= 32'hA65D;
3'b001: number <= 32'hBAB9;
3'b010: number <= 32'h9430;
3'b011: number <= 32'h8BEB;
3'b100: number <= 32'h7CB8;
3'b101: number <= 32'h62F1;
3'b110: number <= 32'h6EF9;
3'b111: number <= 32'h5D5C;
endcase
Related
module task_A(input [15:0]sw, input clk,output reg [3:0] an= 4'b1111,output reg[7:0] seg);
reg [2:0] num = 3'd0;
wire Z,Z1,Z2;
clk_1_47hz(clk,Z1);
clk_762hz(clk,Z2);
reg count=0;
assign Z= (count<5)?(Z1):(Z2);
always # (posedge Z)
begin
num <= (sw[15:0]==16'b1111111111111111)?((num==5 | num==0)?(3'd1):(num+1)):(0);
count <=count+1;
case(num)
3'd0 : begin seg <= 8'b11111111 ; an <= 4'b1111; end
3'd1 : begin seg <= 8'b10000111 ; an <= 4'b0111; end //t
3'd2 : begin seg <= 8'b10001000 ; an <= 4'b1011; end //a
3'd3 : begin seg <= 8'b11001111 ; an <= 4'b1101; end //l
3'd4 : begin seg <= 8'b11111001 ; an <= 4'b1101; end //l
3'd5 : begin seg <= 8'b10010001 ; an <= 4'b1110; end //y
endcase
end
endmodule
I wish to change the clock after the 7 segment display has displayed 'tally' once. So I use count to check. But the clock does not change at all. May I know how to correct it?
count is declared as a 1-bit signal, which is always smaller than 5.
reg count=0;
To accomplish your goal, declare it as a 3-bit signal or more.
And you may also need to set a limit for count, and stop it, if you want to switch to Z2 clock forever after 'tally' is displayed once.
i'm trying to create a 8 bit parallel to serial component that send the data and bit number.
the bit number and the transmitted serial data is not sent at the right time,
please see wave form
module counter
(
input clk,rst,
input [7:0]data,
output reg [7:0]cnt,
output reg data_Tx
);
parameter lim = 7;
always #(posedge clk or negedge rst)
if (!rst)
begin
cnt <= 0;
data_Tx <= 1'b1;
end
else
begin
if (clk)
begin
if (cnt < lim)
begin
data_Tx <= data[cnt];
cnt <= cnt +1;
end
else
cnt <= 0;
end
end
endmodule
please see wave form here
i have marked on the waveform (in blue) the bit numbers that supposed to be transmitted, as you can see they are shifted.
also, in red circle, the data_Tx needs to be '0' when transmitting the first bit from the parallel inputs, but i'ts '1'because of the rst line, how can i fix this situation?
should i use a state machine???
thank you
You have fallen into the standard trap all beginners with HDL have: your signals change after the clock edge. Take a few months of coding and dealing with this becomes second nature.
But before I deal with that: follow Greg's advice and remove the if (clk) from the code.
The first, simple solution, is to move the data_Tx <= data[cnt]; outside the clocked section:
assign data_Tx = data[cnt];
But beware that makes that after a reset (when cnt is zero) the data_Tx bit reflects your data[0] bit. So there is no guarantee that it is 1. Also it will change as soon as a new value is assigned to data.
If you want a synchronous data_Tx output and want the cnt to be inline you have to delay your cnt by a clock cycle:
....
reg [2:0] early_cnt;
always #(posedge clk or negedge rst)
if (!rst)
begin
cnt <= 0;
early_cnt <= 8'h00;
data_Tx <= 1'b1;
end
else
begin
cnt <= early_cnt;
if (early_cnt < lim)
begin
data_Tx <= data[early_cnt];
early_cnt <= early_cnt + 8'h01;
end
else
early_cnt <= 0;
end
I'm trying to make a second counter and millisecond counter using Verilog. The Problem is that whenever I run a simulation, the value of the second counter (clk_1sec) and millisecond counter (clk_1msec) is fixed to 0.
My Simulation shows proper result until 19th line of the code, but the simulation doesn't show the proper result of clk_1sec and clk_1msec (value of those two counters are fixed to 0)
module clk_gen(clk_5k, reset, loopcount, clk_1sec, clk_1msec);
input clk_5k, reset;
output [14:0] loopcount;
output clk_1sec, clk_1msec;
reg [14:0] loopcount;
reg clk_1sec, clk_1msec;
always #(posedge clk_5k or negedge reset)
begin
if (~reset)
begin
clk_1sec <= 0; clk_1msec <= 0; loopcount <= 0;
end
else
loopcount <= loopcount + 2'b10;
begin
if (loopcount += 13'b1001110001000)
clk_1sec = ~clk_1sec;
else if (loopcount += 3'b101)
clk_1msec = ~clk_1msec;
end
end
end
end
endmodule
Expected result is that clk_1sec should change its value when the value of loopcount is loopcount + 5000 (decimal) and clk_1msec should change its value when the value of loopcount is loopcount + 5 (decimal).
There are some misunderstandings in your code:
You are using blocking assignments inside clocked always. You should use only non blocking assignments.
You are using 13 bit constants to operate with a 15 bit register (loopcount). You should use 15 bit constants.
And above all, you are using an improper way to tell if the value of loopcount is multiple of 5 (to count miliseconds). Multiples of something that is not a power of two is difficult to implement in hardware. Either you should use a power of two clock signal (32.768 kHz is a common clock for these applications) or you should use a counter to count cycles to get miliseconds and another one to count miliseconds to get one second.
Assuming a 32.768 kHz clock, your module would go like this:
module clk_gen (
input wire clk32768,
input wire reset,
output reg [15:0] loopcount,
output wire clk_1sec,
output wire clk_1msec
);
assign clk_1sec = loopcount[15]; // 1 exact second (32768 counts)
assign clk_1msec = loopcount[5]; // not quite 1ms, but 0.97ms
always #(posedge clk32768 or negedge reset) begin
if (~reset)
loopcount <= 16'd0;
else
loopcount <= loopcount + 16'd1;
end
endmodule
If you need to stick with a 5KHz clock and/or need precise milisecond measurement (within the limits of your clock oscillator), then you can do as this:
module clk_gen (
input wire clk_5k,
input wire reset,
output reg clk_1sec,
output reg clk_1msec
);
reg [2:0] counter_cycles; // counts from 0 to 4 cycles => 1ms
reg [9:0] counter_msecs; // counts from 0 to 999 msecons => 1s
always #(posedge clk_5k or negedge reset) begin
if (~reset) begin
clk_1sec <= 1'b0;
clk_1msec <= 1'b0;
counter_cycles <= 3'd0;
counter_msecs <= 10'd0;
end
else begin
if (counter_cycles == 3'd4) begin
counter_cycles <= 3'd0;
clk_1msec <= ~clk_1msec;
if (counter_msecs == 10'd999) begin
counter_msecs <= 10'd0;
clk_1sec <= ~clk_1sec;
end
else begin
counter_msecs <= counter_msecs + 10'd1;
end
end
else begin
counter_cycles <= counter_cycles + 3'd1;
end
end
end
endmodule
You can edit/simulate this version at
https://www.edaplayground.com/x/3CjH
The problem is improper nesting of begin/end blocks with the first else. Your indentation does not match what the compiler sees. And I'm sure you meant == instead of +=
Verilog Error
I am trying to learn verilog . This code is made for seven segment led using counter. But I am not able to assign value to nr it gives error. I made a state machine and wish to get next number on seven segment led after each positive clock.
/aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa/
module LED ( nr,clk);
input clk;
output [6:0]nr; //output led seven bit number
reg [6:0]nr;
reg [2:0]state;
always #(posedge clk);
begin
state <= 3'b000; // assigning at each clock
case (state)
3'b000:
begin
nr <= 7'b0000001;
state <= 3'b001;
end
3'b001:
begin
nr <= 7'b0011111;
state <= 3'b010;
end
3'b010:
begin
nr <= 7'b0100101;
state <= 3'b011;
end
3'b011:
begin
nr <= 7'b0001100;
state <= 3'b100;
end
3'b100:
begin
nr <= 7'b1011010;
state <= 3'b101;
end
3'b101:
begin
nr <= 7'b1001000;
state <= 3'b110;
end
3'b110:
begin
nr <= 7'b1000000;
state <= 3'b111;
end
3'b111:
begin
nr <= 7'b0011101;
state <= 3'b000;
end
end
endmodule
always #(posedge clk) no semicolon!
I'm developing a counter in Verilog that cycles through the following series:
0, 1, 3, 7, 6, 4, 0, 1, ...
and resets to 0 on reset_b.
Here is my code so far, it doesn't seem to make it past 3 in the cycle:
module Counter_1(output reg [2: 0] Count, input clock, reset);
reg [2: 0] last;
always #(posedge clock, negedge reset) begin
if (!reset) begin
Count <= 3'b000;
end
else begin
case (last)
3'b000: Count <= 3'b001;
3'b001: Count <= 3'b011;
3'b011: Count <= 3'b111;
3'b111: Count <= 3'b110;
3'b110: Count <= 3'b100;
3'b100: Count <= 3'b000;
endcase
end
last <= Count;
end
endmodule
It is always useful to look at the sequence:
000
001
011
111
110
100
Analyse the pattern and you find the sequence can be made by:
if (!reset)
Count <= 3'b000;
else
Count <= {Count[1:0],~Count[3]};
To follow your method: you can just use the Count as input for the next value. The usage of 'last' is not needed:
case (Count)
3'b000 : Count <= 3'b001;
3'b001 : Count <= 3'b011;
You should certainly be assigning last in the reset block:
if (!reset) begin
last <= 3'b000;
Count <= 3'b000;
end
I'd imagine that will fix your issue, as I don't see any other problems with your code (assuming your clock and reset inputs work correctly and you're using an active high reset).
Also, why are you including reset in your always condition? I believe that your always condition could simply be:
always #(posedge clock) begin