Why does the PL330 always trigger a RX Timeout when reading? - linux

Question

we are using a CycloneV FPGA system with an integrated ARM Cortex-A9 dual core processor system. This processor system is running angstrom linux with a 4.1 kernel and has a pl330 DMA core. We are trying to write a kernel module to use this DMAC to push data into the FPGA fabric and read from it.
Writing to the FPGA works (albeit pretty slow), but everytime we try to read I can see the read transfer taking place, but the linux dmaengine reports a timeout and on kernel-level, the transfer is never finished.
Does somebody know why this might happen? I can comment out the timeout logic and get data out of it, so I'm guessing it might have to do with cache-coherency or something similar.
This is the read function in our kernel module:
static int dma_start_rx(struct platform_device *pdev, unsigned datalen, unsigned char *databuf, u32 burst_size, bool isDecrypt) {
struct mRiddler_dev *pdata = platform_get_drvdata(pdev);
struct dma_chan *dmaChan;
struct dma_slave_config dmaConf;
struct dma_async_tx_descriptor *dmaDesc = NULL;
dmaChan = pdata->dma_rx_chan;
memset(&dmaConf, 0, sizeof(dmaConf)); // Clear memory for DMA config
// Build DMA configuration
dmaConf.direction = DMA_DEV_TO_MEM;
if (isDecrypt)
dmaConf.src_addr = pdata->dma_datareg_phy + RID_DMA_DATA_READ_DECRYPT;
else
dmaConf.src_addr = pdata->dma_datareg_phy + RID_DMA_DATA_READ_ENCRYPT;
#ifdef DEBUG
pr_info("Accessing device address: %u, based on dma_datareg_phy: %u\n", dmaConf.src_addr, pdata->dma_datareg_phy);
#endif
dmaConf.src_addr_width = 8;
dmaConf.src_maxburst = burst_size;
pdata->dma_rx_addr = dma_map_single(&pdev->dev, databuf, datalen, DMA_FROM_DEVICE);
// Error handling
if (dma_mapping_error(&pdev->dev, pdata->dma_rx_addr)) {
pr_err("dma_map_single for RX failed!\n");
return -EINVAL;
}
// Setup slave config
dmaengine_slave_config(dmaChan, &dmaConf);
// Get DMA descriptor
dmaDesc = dmaengine_prep_slave_single(dmaChan, pdata->dma_rx_addr, datalen, dmaConf.direction, DMA_PREP_INTERRUPT);
// Error handling
if (!dmaDesc) {
dma_shutdown(pdata);
return -ENOMEM;
}
// Set callbacks
dmaDesc->callback = dma_rx_done;
dmaDesc->callback_param = pdata;
// Get cookie and submit transfer to queue
pdata->dma_rx_cookie = dmaengine_submit(dmaDesc);
// Error handling
if (dma_submit_error(pdata->dma_rx_cookie))
pr_err("RX cookie error on dmaengine_submit\n");
#ifdef DEBUG
pr_info("Issueing RX transfer to DMA engine...\n");
#endif
// Start DMA
dma_async_issue_pending(dmaChan);
return 0;
}
EDIT: Here's where the timeout is set up and the DMA read function is called:
if (numBytes > 0) {
#ifdef DEBUG
pr_info("Calling dma_start_rx with following values: numBytes=%d, burstSize=%d\n", numBytes, burstSize);
#endif
retVal = dma_start_rx(pdata->pdev, numBytes, pdata->dma_rx_buffer, burstSize, false);
if (retVal) {
pr_err("Error starting RX DMA!\n");
return retVal;
}
if (!wait_for_completion_timeout(&dma_read_complete, msecs_to_jiffies(timeout))) {
pr_err("Timeout while waiting for RX DMA\n");
dmaengine_terminate_all(pdata->dma_rx_chan);
return -ETIMEDOUT;
}
*offset = 0;
}
This is the dmesg output when I try to read from the device:
[ 326.486364] Issueing DMA transfer...
[ 326.489952] DMA TX transfer finished!
[ 335.607286] There are 4 words available in enc_tx FIFO!
[ 335.612497] DMA read 32 > requested bytes 16, adjusting...
[ 335.617992] Now reading 16 bytes in 2 words!
[ 335.622246] Adjusted burstSize/numWords, new values: 2 and 2
[ 335.627898] Calling dma_start_rx with following values: numBytes=16, burstSize=2
[ 335.635283] Accessing device address: 3221225480, based on dma_datareg_phy: 3221225472
[ 335.643168] Issueing RX transfer to DMA engine...
[ 336.643795] Timeout while waiting for RX DMA, cookie: 2