DAC implementation in spartan 3e kit using verilog - verilog

Question

I have written two codes for implementation of DAC in Spartan 3E starter Kit, they seem to be working perfectly in simulation but when i attach them to chipscope and load on board I always get a zero value. I have also noticed that there were no critical warnings.
Code 1:
module dac_state_d(
input dacclk,
input reset,
input [31:0] dacdata,
output reg[31:0] previousdata,
output reg dac_mosi,
output reg dac_miso,
output reg dac_cs,
output reg dac_sck,
output reg dac_clr,
output reg spi_ss_b,
output reg sf_ce0,
output reg fpga_init_b,
output reg amp_cs,
output reg ad_conv,
output reg [2:0] state,
output reg ack
);
integer index=0;
parameter idle=3'b000, ready=3'b001, delay=3'b010, trans=3'b011, read=3'b100, increment=3'b101, check=3'b110;
initial begin//setting different registers on spi bus and initialization
spi_ss_b='b1;
amp_cs='b1;
ad_conv='b0;
sf_ce0='b1;
fpga_init_b='b0;
end
always #(posedge dacclk or posedge reset) begin
if (reset) begin
index<=0;
dac_mosi<=0;
dac_clr<=0;
dac_sck<=0;
dac_cs<=1;
end
else begin
dac_clr<=1;
case(state)
idle: begin
dac_sck <= 0;
dac_cs <= 1;
index <= 0;
dac_mosi <= 0;
ack <= 1;
state <= ready;
end
ready: begin
ack <= 0;
dac_cs <= 0;
dac_sck <= 0;
dac_mosi <= dacdata[31-index];
state <= delay;
end
delay: begin
state <= trans;
end
trans: begin
dac_sck <= 1;
state <= read;
end
read: begin
dac_sck <= 1;
previousdata[31-index]<=dac_miso;
state <= increment;
end
increment: begin
dac_sck <= 1;
index <= index + 1;
state <= check;
end
check: begin
dac_sck <= 1;
if (31-index < 0) begin
state <= idle; end
else begin
state <= ready;
end
end
endcase
end
end
endmodule
with its top module defined as
reg [31:0] dacdata;
wire [31:0] previousdata;
reg [3:0] command, address;
wire dac_miso_w;
assign dac_miso_w=dac_miso;
wire dacclk;
DACCLK clock(.clk(clk),
.dacclk(dacclk)
);
dac_state_d daq_run(.dacclk(dacclk),
.reset(reset),
.dacdata(dacdata),
.previousdata(previousdata),
.dac_mosi(dac_mosi),
.dac_miso(dac_miso_w),
.dac_clr(dac_clr),
.dac_cs(dac_cs),
.spi_ss_b(spi_ss_b),
.sf_ce0(sf_ce0),
.fpga_init_b(fpga_init_b),
.amp_cs(amp_cs),
.ad_conv(ad_conv),
.dac_sck(dac_sck),
.state(state),
.ack(ack)
);
initial begin
command<=4'b0011;
address<=4'b1111;
end
always # (posedge clk) begin
if (ack) begin
dacdata[31:24]<=8'b00000000;
dacdata[23:20]<=command;
dacdata[19:16]<=address;
dacdata[15:4]<=data;
dacdata[3:0]<=4'b0000;
pre_data<=previousdata[15:4];
end
else begin dacdata<=0; end
end
//chipscope-------------------
wire[11:0] D;
wire R;
wire[35:0] CONTROL;
assign D=data;
assign R=reset;
ICON cs_con(.CONTROL0(CONTROL)); //INOUT BUS [35:0]
VIO cs_vio (.CONTROL(CONTROL), // INOUT BUS [35:0]
.ASYNC_IN({pre_data,state,ack}), // IN BUS [12:0]
.ASYNC_OUT({D,R}) // OUT BUS [12:0]
);
//----------------------------------------------------------------------------
endmodule
obviously top module has also I/O port description.
Code 2:
wire dacclk;
DACCLK clock(.clk(clk),
.dacclk(dacclk)
);
initial begin//setting different registers on spi bus and initialization
spi_ss_b='b1;
amp_cs='b1;
ad_conv='b0;
fpga_init_b='b0;
dac_clr=1;
dac_cs=1;
dacstate<=0;
//StrataFLASH must be disabled to prevent it driving the SDI line with its D0 output
//or conflicting with the LCD display
strataflash_oe <= 1;
strataflash_ce <= 1;
strataflash_we <= 1;
end
always#(posedge dacclk) begin
case (dacstate)
//------------------------------Bit 31 to 24 Don't Care----------------------------------
0: begin//idle and allotment cycle(31-->x)
ack=0;
dac_cs=0;
dac_sck=0;
dacstate=1;
end
1: begin//read write cycle (31)
dac_sck=1;
dacstate=2;
end
2: begin//idle and allotment cycle(30-->x)
dacstate=3;
dac_sck=0;
end
3: begin//read write cycle(30)
dac_sck=1;
dacstate=4;
.....
62: begin//idle and allotment cycle(0-->x)
dac_sck=0;
dacstate=63;
end
63: begin//read write cycle(0)
dac_sck=1;
dacstate=64;
end
64: begin//Acknowledging completion of data transfer to DAC
dac_cs=1;
ack=1;
dacstate=65;
end
65: begin if (reset) begin dacstate=0; end
else begin dacstate=65; end end//idle or reset
default: begin dacstate=0; end
endcase
end
endmodule
UCF file i used is as follows
NET "clk" PERIOD = 20.0ns HIGH 50%;
NET "clk" LOC = "C9" | IOSTANDARD = LVTTL;
NET"dac_miso" LOC= "N10" | IOSTANDARD= LVCMOS33 ;
NET"dac_mosi" LOC= "T4" | IOSTANDARD= LVCMOS33 | SLEW= SLOW | DRIVE= 8 ;
NET"dac_sck" LOC= "U16" | IOSTANDARD= LVCMOS33 | SLEW= SLOW | DRIVE= 8 ;
NET"dac_cs" LOC= "N8" | IOSTANDARD= LVCMOS33 | SLEW= SLOW | DRIVE= 8 ;
NET"dac_clr" LOC= "P8" | IOSTANDARD= LVCMOS33 | SLEW= SLOW | DRIVE= 8 ;
NET "fpga_init_b" LOC = "T3" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ;
NET "ad_conv" LOC = "P11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
NET "amp_cs" LOC = "N7" | IOSTANDARD = LVCMOS33 | SLEW = SLOW |DRIVE = 6 ;
NET "spi_ss_b" LOC = "U3" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
NET "sf_ce0" LOC = "D16" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 2;
NET "reset" LOC = "V4" | IOSTANDARD = LVTTL | PULLDOWN;
I don't expect some-one to solve my problem but I feel helpless as i am debugging these codes from past 2 weeks and i am unable to find any problem. It will be really helpful if someone can point me towards error. I also went through some sample codes but as all are written in VHDL hence they were not great help to me. still i tried to match the logic and found it to be the same.

Answer 1

The error in code is very basic, actually in connection to VIO. Inputs can't be connected to VIO as VIO is internal hence need to connect the wire only. Also, there is assignment of input to wire and Wire is reassigned by VIO, which is not acceptable.