For reasons which cannot be avoided (requirements of Qsys), I have several Verilog modules which end up with many ports which would be far easier to work with if they were packed. To try and explain what I mean, here is an example:
module foo #(
COUNT = 4
) (
//Interface 0
input bar_0,
output deadbeef_0,
//Interface 1
input bar_1,
output deadbeef_1,
//Interface 2
input bar_2,
output deadbeef_2,
//Interface 3
input bar_3,
output deadbeef_3,
);
...
endmodule
Now normally one would just make two vectorised ports (e.g. input [COUNT-1:0] bar,), however Qsys cannot cope with this if the signals need to be fed onto different interfaces - you can only select an entire port, not just a bit of one.
As you can imagine, this gets very irritating if internally you need to access the ports in something like a generate loop, and is especially problematic if you have a module with interfaces that have 10 ports which have to be written out 16 times!
What I've been doing up until now would be to add a mapping into the module manually. Again and example to explain - continuing the example above, I'd have something like this in the body of the module:
wire [COUNT-1:0] bar;
wire [COUNT-1:0] deadbeef;
generate
if (COUNT > 0) begin
assign bar[0] = bar_0;
assign deadbeef_0 = deafbeef[0];
end else begin
assign deadbeef_0 = 1'b0; //Terminate!
end
if (COUNT > 1) begin
assign bar[1] = bar_1;
assign deadbeef_1 = deafbeef[1];
end else begin
assign deadbeef_1 = 1'b0; //Terminate!
end
...
endgenerate
// deadbeef[] and bar[] can now be used as arrays, woop.
Even just writing out a couple of the interfaces for only two signals in that example was incredibly tedious!
Every part of the programmer in me is screaming out to stop doing this and that there must be a better way. And that brings me to my question:
Is there a simple way of doing this?
Ideally I'd have some form of loop which generates these mappings for me, generating the signal names from a loop variable. But I'm not sure if this is even possible in Verilog.
Also, just to make things interesting, I have been using hexadecimal for ports to make things easier when writing it out, for example:
input bar_0,
input bar_1,
...
input bar_9,
input bar_a,
input bar_b,
...
Ideally the solution to this would also cope with names like that, but to be honest I could easily convert the names to decimal (bar_10) if it simplifies things.
In case you are wondering, this is made very easy in Qsys to link the interfaces to ports because Qsys uses TCL files to make the mapping. In TCL I can simply use a for loop and concatenate the loop variable to make the names.
I guess, in your case, macro can be used to solve your problem. So, everywhere, in your code, you can use bar as a vector, though it is not.
Define a macro like this :
`define bar(n) bar_``n``
`define deadbeef(n) deadbeef_``n``
You can use now bar as a vector like below:
`bar(0)
`deadbeef(0)
Related
Is their a possibility to access a node in the code using a define macro via string parameters
e.g.
module design
(
input logic signal_in_1_temp,
input logic signal_in_2_temp
);
endmodule
module tb_top;
parameter string signal_names[0:1] = {"in_1","in_2"};
i_design design(.signal_in_1_temp(0),.signal_in_2_temp(0));
`define IN_SIG(IN_NAME,VAL)\
force i_design.signal_\``IN_NAME\``_temp = VAL;
initial begin
\`IN_SIG(signal_name[0],1);
\`IN_SIG(signal_name[1],0);
end
endmodule
In the above the two inputs of the design would need to be accessed via a parameter list and then a macro ...
Compiling the above gives error .... I would want to know if we can access the nodes status or drive them based on the above means ..
The idea is to have a dynamic parameter list given and then to know the status of that list or drive them based on need....
Any suggestions ... please
No, you cannot use string names within the language to build identifier names. Verilog does have a C interface (called VPI) that allows you to access signals by signal name, but that comes at a performance cost which means the signal cannot have certain optimizations and must remain intact.
SystemVerilog has a bind construct that allows you to attach functionality to signals deep inside your design. I wrote a DVCon paper about it.
No, you cannot do it with strings, but you can do it with regular macro arguments.
here is a working example:
`define A(B) \
$display(sig_``B``_sig);
module top;
logic sig_x_sig, sig_hello_sig;
initial begin
`A(x)
`A(hello)
end
endmodule
do not use \ as in your code and do not use empty lines in macro definitions.
I am trying to run different testing procedures inside my testbench and have run them depending on which generate flag I set. Note, the below code is what I am defining to ModelSim as the top level. Here is what I am trying to do:
module testbench
#( parameter FLAG1 = 0, parameter FLAG2 = 1)();
... // code here
generate
if (FLAG1 == 1)
Component1(signals);
else if (FLAG2 == 1)
Component2(signals);
else
// set everything to zero
endgenerate
endmodule
With this, I just want to be able to set the default value of the parameter inside this testbench and run different cases. This compiles fine in ModelSim PE Student Edition 10.4a, but when I go to add the signals from the generated instance name, Modelsim does not recognize that the instance exists?
** Error: (vish-4014) No objects found matching 'spi_tb/uut4/*'.
I figured it out. It does work, modelsim just names the instance genblk[i]/youInstanceNameHere.
I would like to define a parameter MYTYPE using text macro, whose value is passed over by text macro, eg
`define MY_FEATURE(nam,def) parameter nam=def;
and then
`MY_FEATURE(MYTYPE, 1)
But the value is mixed by those who are defined by other text macros, eg
`MY_FEATURE(NEWTYPE, 2)
`MY_FEATURE(MYTYPE, NEWTYPE)
The latter case will not work unless the def in define MY_FEATURE is added with the directive dot.
I need to distinguish this two different cases and automatically expand the macro - only if it is defined, so I came up with this code but I got error.
`define yea 1
`define nop 0
`define MY_FEATURE(nam,def) `ifdef def parameter nam=`def; `else parameter nam=2; `endif
module test;
`MY_FEATURE(MYTYPE,yea)
initial begin
$display("%d",MYTYPE);
end
endmodule
The above code works and gives a 1 as output. However if I write
`MY_FEATURE(MYTYPE,10)
since for other cases I need to assign an actual number to the parameter, then I will get
`ifdef without a macro name - ignored.
My desired result is MYTYPE is assigned as 10.
Is there any way to achieve this? Thanks.
Code can be found here
http://www.edaplayground.com/x/6Jha
I think you are overthinking it. `define creates an directive expression. When when you pass a directive as parameter to another directive you can pass it as `yea.
Here is an example:
`define yea 1
`define nop 0
`define MY_FEATURE(nam,def) parameter nam=def;
module test;
`MY_FEATURE(MYTYPE,`yea)
`MY_FEATURE(MYTYPE2,10)
`MY_FEATURE(MYTYPE3,MYTYPE+MYTYPE2)
initial begin
$display("%d %d %d",MYTYPE, MYTYPE2, MYTYPE3); // displays: 1 10 11
end
endmodule
http://www.edaplayground.com/x/5Pgf
Verilog-AMS (superset of Verilog-A) is a language of its own, derived from Verilog (IEEE Std 1364); according the manual. This means your MY_FEATURE never creates new directives; it creates parameters. Directives and parameters are both treated as constants in simulation but act differently in compile. The `define/parameters relation in Verilog (and Verilog derived languages) is equivalent to C's #define/const relation. Unlike C, to access the value of a `define requires a ` prefix.
Neither directives or parameters cannot start with a numeric value. The first character must be an alpha or underscore (aka [a-zA-Z_]). There for 10 can never be a directives and even trying to use it is illegal syntax. There is noway for the compile to recover from an illegal syntax directive name. This is way I suggested passing `yea instead of yea.
If someone build you a nice model, then it should come with equally nice documentation or some way of getting support.
Let's say I have some define macro, and then some other wire that is defined.
What does it mean when I have them like this? Is it just meaning to take the 2 LSBs from the wire?
`define A_DEFINE 32
// *SOME CODE IN HERE*
output [`A_DEFINE-1:0] my_out_wire;
// *MORE CODE HERE*
I can't seem to find any explanation of this meaning.
The syntax `define A_DEFINE 32 declares a macro called A_DEFINE. A macro is a thing you can use for text replacement in your code.
The syntax `A_DEFINE means expand the A_DEFINE macro. This is essentially taking the value of A_DEFINE and copying in the place where the macro is expanded.
The preprocessor does this for you. In essence, you'll end up with:
// *SOME CODE IN HERE*
output [32-1:0] my_out_wire;
// *MORE CODE HERE*
Defines are handy if you need to have a configurable element in your code. This way if you have multiple signals that are supposed to be as wide, you just use the define. In case you need to change from 32 to 64, you just modify the define and that's it.
Also have a look at the SystemVerilog parameter. This might also be helpful.
I'm often declaring bit widths like this:
parameter FOO_BITS=4;
reg [(FOO_BITS-1):0] foo_1;
reg [(FOO_BITS-1):0] foo_2;
That is, I declare a parameter for a width, and then I declare a data type whose width is that parameter minus one.
The - 1 syntax is quite an eyesore to me. I could just say that FOO_BITS=3, but 4 more easily conveys the intent of the parameter to the reader: foo data types should have a width of 4 bits.
Is this just a Verilog fact of life? Is there any way to make this a little cleaner and less repetitive?
Unfortunately you're not likely to get rid of the -1s completely, unless you want to change the meaning of FOO_BITS or index from 0, neither of which are recommended - they go against convention somewhat and will make it harder for anybody else to understand your code. You could remove the brackets though which are superfluous and make the line harder to parse.
Another way to tidy things up is to use typedefs:
parameter FOO_BITS = 32;
typedef logic [FOO_BITS-1:0] word_t;
word_t foo_1;
word_t foo_2;
I find this also makes code more readable when using multi-dimensional arrays:
word_t foo_3;
word_t [N_WORDS-1:0] foo_array;
I can't think of a way to get rid of -1 either, but just like any other repetitive construct, you can hide it behind a macro:
`define RANGE(_WIDTH_) _WIDTH_-1:0
Now you can define your array as:
reg [`RANGE(FOO_BITS)] foo_1;
Not sure if this is less of an eyesore, but it requires the reader to refer to the definition of RANGE.