Programming help for Verilog beginner. Debugging in ISE - verilog

Question

I have experience in VHDL and SystemC, and now I'm training to learn Verilog, but I'm having trouble getting started.
I'm currently trying to make a 8 bit adder.
module alu(
input [7:0] a,
input [7:0] b,
input clk,
input op,
output reg [7:0] out,
output reg overflow
);
integer myA;
integer myB;
always #(negedge clk)
begin
myA = a;
myB = b;
overflow = 0;
if (op == 0) begin
//Subtract
out = myA - myB;
if (myA - myB <0) begin
overflow = 1;
end
end
else begin
//Add
out = myA + myB;
if (myA + myB > 255) begin
overflow = 1;
end
end
end
endmodule
But in testing it doesn't work properly.
I used ISE to generate a test bench, and since I don't know how to setup a clock, I set it up manually:
// Add stimulus here
a = 255;
b = 45;
clk = 1;
op = 1;
#100
clk = 0;
// Add stimulus here
a = 0;
b = 255;
clk = 1;
op = 1;
#100
clk = 0;
// Add stimulus here
a = 255;
b = 0;
clk = 1;
op = 0;
#100
clk = 0;
// Add stimulus here
a = 90;
b = 45;
clk = 1;
op = 1;
#100
clk = 0;
The last instruction, 45+90 gives me the correct result, but every other result gives me 0.
I've tried several variations of the main if, but there always errors in the output.
if (op == 0) begin
out = a + b;
if (myA-myB <0) begin
//overflow
out = 7;
end
end else begin
out = a-b;
if (myA+myB>255) begin
//overflow
out = 8;
end
end
Here's the full test bench code. Edited to include #100 between clk = 0 and clk = 1.
`timescale 1ns / 1ps
module a;
// Inputs
reg [7:0] a;
reg [7:0] b;
reg clk;
reg op;
// Outputs
wire [7:0] out;
// Instantiate the Unit Under Test (UUT)
alu uut (
.a(a),
.b(b),
.clk(clk),
.op(op),
.out(out)
);
initial begin
// Initialize Inputs
a = 0;
b = 0;
clk = 0;
op = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
a = 55;
b = 45;
clk = 1;
op = 1;
#100
clk = 0;
#100
// Add stimulus here
a = 255;
b = 45;
clk = 1;
op = 1;
#100
clk = 0;
#100
// Add stimulus here
a = 0;
b = 255;
clk = 1;
op = 1;
#100
clk = 0;
#100
// Add stimulus here
a = 255;
b = 0;
clk = 1;
op = 0;
#100
clk = 0;
#100
// Add stimulus here
a = 90;
b = 45;
clk = 1;
op = 1;
#100
clk = 0;
#100
end
endmodule

Answer 1

#X in Verilog means "delay X time steps before continuing". So in your code
#100
clk = 0;
// Add stimulus here
a = 255;
b = 0;
clk = 1;
there's no delay between the clock going low and going high again, which might be your problem. Try adding a #100 somewhere between clk = 0; and clk = 1;

Answer 2

Just a tip. I think in most cases the clock is created in an always block and then the inputs are changed in another initial block so
always begin
#5 clk = ~ clk; // here the clock period is 10
end
initial begin
clk = 0;
a = 255;
b = 45;
op = 1;
#10;
a = 90;
b = 45;
op = 1;
end