I am writing a program in verilog. Total 3 AND Gates, the output of first 2 AND Gates is input to the 3rd Gate, and i am required the output of 3rd Gate. Please let me know what is the problem with my program. I am attaching my Program
//enter Top Module
module TOP;
wire a,b;
reg out;
initial
begin
#3 a=1;
#3 b=1;
#3 b=0;
end
Two_AND s(a,b,out);
endmodule
//.....................
//Main Program
module Two_AND (a,b,out);
input a,b;
output out;
reg out;
and g1(out1,a,b);
and g2(out2,b,c);
and g3(out3,out1,out2);
endmodule
In module Two_AND (a,b,out); you have these lines:
and g2(out2,b,c);
c is not defined.
out1, out2 and out3 are also not defined but are outputs and will be created as 1 bit wires by default which is ok in this instance.
but your output out is not driven, where you have used out3 you need to use out.
module Two_AND (
input a,
input b,
input c,
output out
);
wire out1,out2;
and g1(out1,a,b);
and g2(out2,b,c);
and g3(out,out1,out2);
endmodule
#Morgan is right.
However, the error you get is because there is something wrong with your TOP module.
You should have defined a and b as reg and out as wire.
Only regs can be assigned within an initial or always block.
And outputs of modules should be connected to wires.
Also, since an input c is added to your module, you should consider it while you are instantiating your Two_AND in your TOP module.
I think the previous answers were very instructive and helpful. I only want to add a small tip. I recommend you that always add `default_nettype none to your verilog codes. for example you have used "out1" and "out2" wires but you haven't define them. if you don't want to be confused, you should add that to your codes.
Related
I'm confused about connection, I want to use ALU to call RippleCarry module, and I need to do branch without always block and Procedure Assignment.
I don't know what method is best. I see others have written in TestBench.v or ALU.v.
Here's my code.
ALU.v
module ALU( Signal, a, b, Output );
input [31:0] a, b;
input [5:0] Signal;
output [31:0] Output;
// write here ? or write into test bench?
// if Signal is 6'd35, do RippleCarry.
/*RippleCarry RC( .a(a), .b(b), .Sum(Output) ); */
endmodule
RippleCarray.v
module RippleCarry(
input [31:0] a, b,
input Cin,
output Cout,
output [31:0] Sum
);
In verilog, modules are not called, but instantiated. Unlike traditional programming, verilog is a hardware descriptive language; meaning it is code describing hardware, not specifying instructions to be run by a cpu as you do in typically programming languages. Hardware doesn't materialize and dematerialize when signals take on different values; the control signals simply define which of many different data paths is connected between input and output.
In your case, you wouldnt write something like this:
module ALU(...)
if (Signal == 6'd35) begin
RippleCarry RC(...);
end
endmodule
Since Signal is a control line that changes value as the hardware runs, this would imply the ripple carry adder exists when the Signal is 35 and disappears when it's not.
Instead, the adder should be instantiated, it exists in the design and it always there. The problem now is to direct it's output to the output of the ALU only when Signal is 35.
module ALU(input [5:0] Signal,
input [31:0] a, b,
output reg [31:0] Output); // Note, I made Output a reg so I can use always, it doesn't mean it's actually a register
wire [31:0] rcOutput;
// Instantiate the RC adder so it exists in the hardware
RippleCarry RC(.a(a), .b(b), .Sum(rcOutput));
// Direct the output of the RippleCarry adder to the output only when signal is 35, otherwise just leave it at 0.
// Use switch here to make it easy to add more operations later
always #(*) begin
Output = 32'd0; // default
case (Signal)
6'd35: Output = rcOutput; // rc add
endcase
end
endmodule
Edit: I see now you want to do it without using always or assign, which doesn't change the fundamental design but makes it more obscure and less scalable, which is why I'm leaving the above as a reference. In the case we only have one op code for signal, we can simply implement the logic that compares signal to 35 and masks output if not equal in gates:
// Replace the always block with the below, though it's certainly not as nice, it's a possible implementation of that always block in gates
wire [5:0] SignalN;
wire SignalIs35;
not g1[5:0](SignalN, Signal);
// 35 is 100011 in binary, so see if Signal is that value
and g2(SignalIs35, Signal[5], SignalN[4], SignalN[3], SignalN[2], Signal[1], Signal[0]);
and g3[31:0](Output, rcOutput, {32{SignalIs35}});
I am trying to wire a Verilog Structural description of an Edge-triggered T flip-flop with an synchronous reset (R). Here is the circuit for this element:
Now assume that I have already written the behavioral description for each block in this schematic , so here is my structural description for this circuit by instantiation of each of this blocks in the circuit:
module edge_trig_flipflop_structure (
input x,y,clk,
output q,
wire a,b,c,d
);
inv u1(c,q);
mux_2x1 u2 (q,c,x,a);
inv u3(d,y);
and_2_1 u4(b,a,d);
d_flipflop u5(b,clk,q);
endmodule
Is this a good efficient code for this circuit? In other words, do I really need the two extra wires used for the inverters which are the wires c and d Or, is there another efficient way to write this code?
Edit : Here is the code for each component to know the order of ports in the declaration of each component
module mux_2x1 (
input a,
input b,
input sel,
output reg c
);
always # (*) begin
case ( sel)
1'b0: c=a;
1'b1: c=b;
default : $dispaly ("error");
endcase
end
endmodule
module d_flipflop ( input d,clk , output reg q);
always # (posedge clk ) begin
q=d;
end
endmodule
module inv(output reg b, input a);
always # (a) begin
b=~a;
end
endmodule
module and_2_1 ( output reg c,input a,b);
always #(a or b) begin
if (a==1'b1 & b==1'b1)
c= 1'b1;
else
c=1'b0;
end
endmodule
By default, Verilog does not require you to declare all signals. If signals appear in port connections, they will implicitly be 1-bit wire types.
However, it is good practice to declare all signals explicitly with wire, as you have done.
You could also change the default behavior and require explicitly declared signals using this compiler directive:
`default_nettype none
Since you are also concerned about connections, it is a good practice to make connections by name instead of connections by position. It is more verbose, but it will help avoid simple connection errors. For example:
inv u1 (.b(c), .a(q));
I got compile errors on your module header. You probably meant to code it this way:
module edge_trig_flipflop_structure (
input x,y,clk,
output q
);
wire a,b,c,d;
module tff(t,i,qbprev,q,qb);
input t,i,qbprev;
output q,qb;
wire q,qb,w1;
begin
assign w1=qbprev;
if(w1==1)begin
not n1(i,i);
end
assign q=i;
not n2(qb,i);
end
endmodule
module counter(a,b,c,cin,x0,x1,x2);
input a,b,c,cin;
output x0,x1,x2;
reg a,b,c,x0,x1,x2,temp,q,qb;
always#(posedge cin)
begin
tff t1(.t(1) ,.i(a),.qbprev(1),.q(),.qb());
x0=q;
temp=qb;
tff t2(.t(1) ,.i(b),.qbprev(temp),.q(),.qb());
x1=q;
temp=qb;
tff t3(.t(1) ,.i(c),.qbprev(temp),.q(),.qb());
x2=q;
a=x0;
b=x1;
c=x2;
end
endmodule
This is my code in verilog. My inputs are - the initial state - a,b,c and cin
I get many errors with the first of them being "w1 is not a constant" What doesn this mean?
I also get error "Non-net port a cannot be of mode input" But I want a to be an input!
Thank you.
Modules are instantiated as pieces of hardware. They are not software calls, and you can not create and destroy hardware on the fly therefore:
if(w1==1)begin
not n1(i,i);
end
With that in mind I hope that you can see that unless w1 is a constant parameter, and this is a 'generate if' What your describing does not make sense.
instance n1 is not called or created as required, it must always exist.
Also you have the input and output connected to i. i represent a physical wire it can not be i and not i. these need to be different names to represent different physical wires.
In your second module you have :
input a,b,c,cin;
// ...
reg a,b,c; //...
Inputs can not be regs as the warning says, just do not declare them as regs for this.
input a,b,c,cin;
output x0,x1,x2;
reg x0,x1,x2,temp,q,qb;
I would like to know if there is a syntax in Verilog to access a wire in a sub-module without making that wire an output.
For example, if have the following modules:
module Module_Sub(a,b);
input a,b;
wire c;
...
endmodule
module Module_Top(d, e);
input d,e;
wire f;
Module_Sub sm(d,e);
...
endmodule
Now, I want to access the wire 'c' in the instance 'sm' from the scope of Module_Top.
Is there a way to do it?
maybe something like:
assign f = sm/c;
(This syntax obviously didn't work for me).
P.S:
I know this isn't the best practice, but in my case it will make things a lot easier.
Thanks!
edit: I want it for a synthesis-able code.
You were very close. Use dot, not slash:
module Module_Sub(a,b);
input a,b;
wire c;
endmodule
module Module_Top(d, e);
input d,e;
wire f = sm.c;
Module_Sub sm(d,e);
endmodule
Refer to IEEE Std 1800-2012, section 23.7 "Member selects and hierarchical names".
I'm having problems on how to create a test module for the following Verilog code:
module Multiplier_4bit(output [8:0] y, input [3:0] i1, input [3:0] i2);
assign y=i1*i2;
endmodule
I thought of the following test module:
module M4_Tester
reg [3:0] i1;
reg [3:0] i2;
wire [9:0] y;
initial begin
i1=5;
i2=3;
$finish();
Multiplier_4bit device1(
.out(y),
.in0(i1),
.in1(i2)
);
endmodule
Please correct me if I'm wrong and sorry for bad english, as I am not a native speaker.
Thanks in advance.
You cannot instantiate a module inside of a begin block (put the multiplier somewhere outside of your initial begin block.
You have no corresponding end which closes the initial begin block.
Your simulation will terminate instantly because there is no delay between setting the values and the $finish. Put some nominal time delay before the simulation finishes with #10 $finish().
Next time please clarify your question before asking, and post the actual error messages you are receiving.