Independent Nexys 4 clocks desynchronizing over time - verilog

Question

We are developing a program which needs synchronized clocks on two devices to measure the fly time of ultrasound signals.
The problem is that when we synthesize the program and test it on two independent Nexys4 FPGAs the distance tends to decrease over time (0.13 cm/s). This ratio is constant, and always decreasing, leading us to think that the problem is in the code.
And when we synthesize the program in only one Nexys 4, no decrease is seen over time.
We have a module to listen for signals (3 signals per slave, and 3 slaves) called dataListener: the signal SendCommand is the control signal for an UART module which sends the direction and command to an SRF02 ultrasound, this module is exactly the same on both devices.
module dataListener(
input mclk,
input clkSync,
input reset,
input rxDataRdy,
output wire[7:0] command,
output reg[7:0] direction,
output reg read,
output reg sendCommand,
output reg dataChanged,
output reg [1:0] slave,
output reg [1:0] sensor
);
parameter dir0 = 8'd0;
parameter dir1 = 8'd3;
parameter dir2 = 8'd6;
parameter rangingCommand = 8'd87;
parameter readCommand = 8'd94;
//parameter clkTime = 0.000000001; // 1ns Simulation // 10ns FPGA
//parameter windowTime = 0.08; // 80 ms
//parameter listenTime = 0.07; // 70ms
parameter windowCyclesDuration = 8000000;
parameter listenCyclesDuration = 7000000;
reg [54:0] windowCounter;
reg emitSent;
reg readSent;
reg slave1;
reg slave2;
reg slave3;
assign command = emitSent ? readCommand : rangingCommand;
///////////////////////////////////////////////////////////////////
always #(posedge mclk) begin
if( reset )begin
sensor <= 2'b0;
windowCounter <= 55'b0;
emitSent <= 0;
readSent <= 0;
slave <=0;
end else begin
if( clkSync ) begin
if( windowCounter >= windowCyclesDuration )begin //Window ended
windowCounter <= 55'b0; //resetCounter
emitSent <= 0;
readSent <= 0;
if( sensor == 2'd2 )begin
sensor <= 2'b0;
if(slave == 2'd2)
slave <= 2'b0;
else
slave <= slave+1'b1;
end else begin
sensor <= sensor + 1'b1;
end
end else begin
windowCounter <= windowCounter + 1'b1; //Window in process
if(!emitSent)begin
sendCommand <= 1;
end
else if( (windowCounter >= listenCyclesDuration) && !readSent)begin //listen done, time to send the read command
sendCommand <= 1;
end
end
if(sendCommand)begin
sendCommand <= 0; //Shut down "sendCommand" signal.
if(!emitSent)
emitSent <= 1;
else
readSent <= 1;
end
end
/// Process incoming data
if( rxDataRdy )begin
read <= 1;
end else if( read )begin
read <= 0;
end
end
end
//////////////////////////////////////////////////////////////////
always #( sensor ) begin
case(sensor)
2'd0: begin
direction <= dir0;
end
2'd1: begin
direction <= dir1;
end
2'd2: begin
direction <= dir2;
end
default: begin
direction <= dir0;
end
endcase
end
endmodule
A module on the slave device which sends the commands:
module slave(
input mclk,
input clkSync,
input reset,
output [7:0] command,
output [7:0] direction,
output reg sendCommand,
output inWindow
);
parameter numSlave = 2'b0; //Between 0-2
parameter dir=8'd0; //Depends on the slaves direction
parameter comm=8'd92;
assign command = comm;
assign direction = dir;
parameter windowCyclesDuration = 8000000;
reg [54:0] windowCounter;
reg [1:0] sensor, slave;
reg commandSent;
assign inWindow = (slave == numSlave);
always #(posedge mclk) begin
if( reset )begin
windowCounter <= 55'b0;
sendCommand <=0;
commandSent <= 1;
slave <= 2'b0;
sensor <= 2'b0;
end else begin
if( clkSync ) begin
if( windowCounter >= windowCyclesDuration )begin //Window ended
windowCounter <= 55'b0; //resetCounter
commandSent <= 0;
if( sensor == 2'd2 )begin
sensor <= 2'b0;
if(slave == 2'd2)
slave <= 2'b0;
else
slave <= slave + 1'b1;
end else begin
sensor <= sensor + 1'b1;
end
end else begin
windowCounter <= windowCounter + 1'b1; //Window in process
if( inWindow && !commandSent)begin //im in my window and command not sent yet
sendCommand <= 1;//send when a new window is about to begin
commandSent <= 1;
end
end
if(sendCommand)begin
sendCommand <= 0; //Shut down "sendCommand" signal.
end
end
end
end
endmodule
The signal clkSync is only activated when both devices are 'Sync', which happend only at the start of functioning through a cable which is then remove to allow movement.
Here is the sync module of the master:
module SyncM(
input mclk,
input reset,
input response1,
input response2,
input response3,
output reg call1,
output reg call2,
output reg call3,
output reg clkSync,
output reg slave1,
output reg slave2,
output reg slave3
);
always # (posedge mclk) begin
if(reset)begin
clkSync <= 0;
slave1 <= 0;
slave2 <= 0;
slave3 <= 0;
call1 <= 0;
call2 <= 0;
call3 <= 0;
end else begin
if( btn && !call1 )begin
call1 <= 1;
call2 <= 1;
call3 <= 1;
clkSync <= 1;
end
if(response1)
slave1 <= 1;
if(response2)
slave2 <= 1;
if(response3)
slave3 <= 1;
end
end
endmodule
And the slave sync module, the call signal is send from the master to slave by a cable.
`timescale 1ns / 1ps
module SyncS(
input reset,
input call,
output reg clkSync,
output reg response
);
always # (reset or call) begin
if(reset) begin
clkSync <= 0;
response <= 0;
end else begin
if (call) begin
response <= 1;
clkSync <= 1;
end
end
end
endmodule

Answer 1

I haven't understand all of your code. But, the problems seems to be, that you rely on the external oscillator on your FPGA board. If you use two boards, both oscillators will not run on exactly the same frequency. So, if you compensate for the phase shift right only once after startup, the clocks will desynchronize after some time. That's why it worked with just one board.
There are two possible solutions:
Use just one clock source (oscillator) and forward the clock to other board.
Periodically compensate for phase shifts.
Both solutions require a more or less steady connection between both boards.