This code should dispaly S for 1 sec then turn off for 1 sec and then dispaly G for 1 sec and then turn of for 1 sec and then display S for 1 sec and so on.
The problem is I am getting S then off then G then off then G then off and so on. I believe the error in the hex7segm module but I could not find a solution. Any help would be appreciated
Here is the code:
module asqw (output wire [6:0]a2g,output wire [3:0]AN,input wire fastclk);
wire slowclk;
slow_clock xx(fastclk,slowclk);
hex7segm zz(slowclk,a2g,AN);
endmodule
moduleslow_clock (input wire fastclk,output wire slowclk);
reg[27:0]period_count=0;
always#(posedge fastclk)
begin
period_count<=period_count+1;
end
assign slowclk=period_count[27];
endmodule
module hex7segm (input wire slowclk,
output reg [6:0]a2g,
output reg [3:0]AN
);
reg[1:0]x;
reg[1:0]y=0;
always#(*)
begin
if(slowclk)
begin
x=y;
AN= 4'b1110;
y=y+1;
if(y==2) y=0;
else
x=2;
AN= 4'b1110;
end
case(x)
0: a2g=7'b0100100;
1: a2g=7'b0100000;
2: a2g=7'b1111111;
default: a2g=7'b0100100;
endcase
end
endmodule
Hi probably a little bit late to answer but here it is: The main problem is that you are mixing combinational and sequential logic. You need to separate these two. Moreover, I couldn't see why your new clock has a duty cycle of 50%.
Top module:
module asqw (
output [6:0]a2g,
input wire fastclk);
wire slowclk;
slow_clock xx(fastclk,slowclk);
hex7segm zz(slowclk,a2g);
endmodule
Seven Segment Driver:
module hex7segm (
input wire slowclk,
output reg [6:0]a2g
);
localparam S = 7'b0100100;
localparam G = 7'b0100000;
localparam OFF = 7'b1111111;
reg [2:0] state = 0;
always # (posedge slowclk)
begin
state <= (state == 5) ? 0 : state + 3'b1;
end
always # (*)
begin
case(state)
0: a2g <= S;
2: a2g <= G;
4: a2g <= S;
default: a2g <= OFF;
endcase
end
endmodule
Slow clock:
module slow_clock (
input wire fastclk,
output reg slowclk = 0
);
reg[27:0]period_count = 0;
always#(posedge fastclk)
begin
period_count <= (period_count == 25000000) ? 0 : period_count+ 28'b1;
slowclk <= (period_count == 25000000) ? ~slowclk : slowclk;
end
endmodule
Related
I am trying to create a second clk counter using a 100 MHz clk input, but when I simulate the clk divider, it just shows the output as an X even though the clk input is correct. What could I be doing wrong?
1 second clk divider:
module clkdiv(
input clk,
input [25:0] terminalcount,
output reg clk_div
);
reg [25:0] count;
wire tc;
assign tc = (count == terminalcount);
always # (posedge(clk)) begin
if (tc) count <= 0;
else count <= count + 1;
end
always # (posedge(clk)) begin
if (tc) clk_div = !clk_div;
end
endmodule
Test Bench:
module clockdivTB;
// inputs
reg clk; // make 100 MHz -- T = 10 ns
// outputs
wire newclk;
// second clock -- connect test signals to clkdiv
clkdiv slowclkCUT (
.clk(clk),
.terminalcount(50000000-1), // 1 Hz
.clk_div(newclk)
);
// initialize inputs
initial begin
clk = 0;
// create input clock 100MHz
forever #5 clk = ~clk;
end
endmodule
Result:
The output is X because reg types are initialized to X (unknown). You need to initialize the output to a known value. For simulation purposes, you can set clk_div and count to 0 as follows:
module clkdiv(
input clk,
input [25:0] terminalcount,
output reg clk_div = 0
);
reg [25:0] count = 0;
However, if you want to synthesize your logic, you likely need to add a reset input. You can drive the input from your testbench.
module clkdiv(
input reset,
input clk,
input [25:0] terminalcount,
output reg clk_div
);
reg [25:0] count;
wire tc;
assign tc = (count == terminalcount);
always # (posedge(clk)) begin
if (reset) count <= 0;
else if (tc) count <= 0;
else count <= count + 1;
end
always # (posedge(clk)) begin
if (reset) clk_div <= 0;
else if (tc) clk_div <= !clk_div;
end
endmodule
I can't figure out why is it that when I set the clock frequency from 50MHz to 100MHz, by changing the clk period to 5 in the testbench, my output transmit and receive data stays at 0. Can anyone enlighten me on this? I need my clock frequency to be 100MHz. Your help will be much appreciated.
Testbench
`timescale 1ns / 1ps
module uart_tx_test();
parameter periodCLK_2 = 5;
parameter perioddump = 10;
parameter delay = 1;
parameter delay_in = 2;
reg CLK_TB = 0 ;
reg RSTN ;
reg [7:0] data = 0;
reg clk = 0;
reg enable = 0;
wire tx_busy;
wire rdy;
wire [7:0] rxdata;
wire loopback;
reg rdy_clr = 0;
uart test_uart(.din(data),
.wr_en(enable),
.clk_50m(clk),
.tx(loopback),
.tx_busy(tx_busy),
.rx(loopback),
.rdy(rdy),
.rdy_clr(rdy_clr),
.dout(rxdata));
initial begin
// $dumpfile("uart.vcd");
$dumpvars(0, uart_tx_test);
enable <= 1'b1;
#2 enable <= 1'b0;
end
always begin
#5 clk = ~clk; //I set period to 5; period was 1 previously.
end
always #(posedge rdy) begin
#2 rdy_clr <= 1;
#2 rdy_clr <= 0;
if (rxdata != data) begin
$display("FAIL: rx data %x does not match tx %x", rxdata, data);
$finish;
end else begin
if (rxdata == 8'hff) begin
$display("SUCCESS: all bytes verified");
$finish;
end
data <= data + 1'b1;
enable <= 1'b1;
#2 enable <= 1'b0;
end
end
endmodule
Design Sources
module uart(
input wire [7:0] din,
input wire wr_en,
input wire clk_50m,
output wire tx,
output wire tx_busy,
input wire rx,
input wire rdy_clr,
output wire rdy,
output wire [7:0] dout
);
wire rxclk_en, txclk_en;
baud_rate_gen uart_baud(
.clk_50m(clk_50m),
.rxclk_en(rxclk_en),
.txclk_en(txclk_en)
);
transmitter uart_tx(
.tx(tx),
.din(din),
.clk_50m(clk_50m),
.clken(txclk_en),
.wr_en(wr_en),
.tx_busy(tx_busy)
);
receiver uart_rx(
.rx(rx),
.data(dout),
.clk_50m(clk_50m),
.clken(rxclk_en),
.rdy(rdy),
.rdy_clr(rdy_clr)
);
endmodule
/*
* Hacky baud rate generator to divide a 50MHz clock into a 9600 baud
* rx/tx pair where the rx clcken oversamples by 16x.
*/
module baud_rate_gen(input wire clk_50m,
output wire rxclk_en,
output wire txclk_en);
parameter RX_ACC_MAX = 100000000 / (9600 * 16);
parameter TX_ACC_MAX = 100000000 / 9600;
parameter RX_ACC_WIDTH = $clog2(RX_ACC_MAX);
parameter TX_ACC_WIDTH = $clog2(TX_ACC_MAX);
reg [RX_ACC_WIDTH - 1:0] rx_acc = 0;
reg [TX_ACC_WIDTH - 1:0] tx_acc = 0;
assign rxclk_en = (rx_acc == 5'd0);
assign txclk_en = (tx_acc == 9'd0);
always #(posedge clk_50m) begin
if (rx_acc == RX_ACC_MAX[RX_ACC_WIDTH - 1:0])
rx_acc <= 0;
else
rx_acc <= rx_acc + 5'b1;
end
always #(posedge clk_50m) begin
if (tx_acc == TX_ACC_MAX[TX_ACC_WIDTH - 1:0])
tx_acc <= 0;
else
tx_acc <= tx_acc + 9'b1;
end
endmodule
module transmitter(
input wire [7:0] din,
input wire wr_en,
input wire clk_50m,
input wire clken,
output reg tx,
output wire tx_busy
);
initial begin
tx = 1'b1;
end
parameter STATE_IDLE = 2'b00;
parameter STATE_START = 2'b01;
parameter STATE_DATA = 2'b10;
parameter STATE_STOP = 2'b11;
reg [7:0] data = 8'h00;
reg [2:0] bitpos = 3'h0;
reg [1:0] state = STATE_IDLE;
always #(posedge clk_50m) begin
case (state)
STATE_IDLE: begin
if (wr_en) begin
state <= STATE_START;
data <= din;
bitpos <= 3'h0;
end
end
STATE_START: begin
if (clken) begin
tx <= 1'b0;
state <= STATE_DATA;
end
end
STATE_DATA: begin
if (clken) begin
if (bitpos == 3'h7)
state <= STATE_STOP;
else
bitpos <= bitpos + 3'h1;
tx <= data[bitpos];
end
end
STATE_STOP: begin
if (clken) begin
tx <= 1'b1;
state <= STATE_IDLE;
end
end
default: begin
tx <= 1'b1;
state <= STATE_IDLE;
end
endcase
end
assign tx_busy = (state != STATE_IDLE);
endmodule
module receiver(
input wire rx,
input wire rdy_clr,
input wire clk_50m,
input wire clken,
output reg rdy,
output reg [7:0] data
);
initial begin
rdy = 0;
data = 8'b0;
end
parameter RX_STATE_START = 2'b00;
parameter RX_STATE_DATA = 2'b01;
parameter RX_STATE_STOP = 2'b10;
reg [1:0] state = RX_STATE_START;
reg [3:0] sample = 0;
reg [3:0] bitpos = 0;
reg [7:0] scratch = 8'b0;
always #(posedge clk_50m) begin
if (rdy_clr)
rdy <= 0;
if (clken) begin
case (state)
RX_STATE_START: begin
/*
* Start counting from the first low sample, once we've
* sampled a full bit, start collecting data bits.
*/
if (!rx || sample != 0)
sample <= sample + 4'b1;
if (sample == 15) begin
state <= RX_STATE_DATA;
bitpos <= 0;
sample <= 0;
scratch <= 0;
end
end
RX_STATE_DATA: begin
sample <= sample + 4'b1;
if (sample == 4'h8) begin
scratch[bitpos[2:0]] <= rx;
bitpos <= bitpos + 4'b1;
end
if (bitpos == 8 && sample == 15)
state <= RX_STATE_STOP;
end
RX_STATE_STOP: begin
/*
* The baud clock may not be running at exactly the
* same rate as the transmitter. If we thing that
* we're at least half way into the stop bit, allow
* transition into handling the next start bit.
*/
if (sample == 15 || (sample >= 8 && !rx)) begin
state <= RX_STATE_START;
data <= scratch;
rdy <= 1'b1;
sample <= 0;
end else begin
sample <= sample + 4'b1;
end
end
default: begin
state <= RX_STATE_START;
end
endcase
end
end
endmodule
You need to scale all your other delays accordingly. Change all your #2 to #10, then you will see the SUCCESS: all bytes verified message.
With your original clock delay of #1, your other input signal pulses (enable and rdy_clr) were wide enough for your uart design module to sample properly. For example, on the 1st posedge of clk, your design properly sampled the enable input as 1, which started the TX state machine.
You increased the clock period by a factor of 5 when you changed the delay from #1 to #5. However, your enable pulse stayed the same width as before, which means that the design sampled enable as 0, not 1. So your TX state machine stayed in the IDLE state. By changing the enable delay from #2 to #10, you are able to properly sample enable as 1.
You can easily prove this to yourself by dumping a VCD file, and viewing the waveforms inside the design.
You could replace the numeric delays with a parameter to make it easier to change to different frequencies.
Note: You stated the clk delay was originally #1. This gives the clk signal a period of 2ns, which is 500MHz, not 50MHz.
I wrote a verilog code for a seven segment display controller as part of my assignment, but in the simulation, i get the following error:
Can someone please resolve this issue? I have attached the following verilog modules:
1.Main controller code
module top(switch, button,clk,anode,cathode);
input wire clk;
input wire[7:0] switch;
input wire[3:0] button;
output wire [3:0] anode;
output wire [7:0] cathode;
wire refreshclock;
wire[1:0] refreshcounter;
wire[3:0] MUXED_digit;
//to instantiate clockmodule here, do this..
clock_module refreshclock_generator (.clk(clk), .sclk(refreshclock));
//to instantaiate seven segment controller modules..
refresh_counter R1 (.refreshclock(refreshclock), .refreshcounter(refreshcounter));
anode_control A1 ( .refreshcounter(refreshcounter), .anode(anode));
bcd_control B1( .digit1(switch[3:0]), .digit2(switch[7:4]),.digit3(button[3:0]), .digit4(button[3:0]),.refreshcounter(refreshcounter), .MUXED_digit(MUXED_digit));
bcd_7seg_case BS1 (.bcd(bcd), .S(S));
endmodule
Clock divider code
module clock_module(t_count,sclk,rst,en,clk);
parameter n=19;
parameter Nc=400000;
input rst;
input en;
input clk;
output reg [n-1:0]t_count;
output reg sclk;
always#(posedge clk or posedge rst) //on FPGA, clock won't start until rst is also pressed. If rst not pressed, then value of N doesn't go into t_count, so at that moment, t_count would be giving us garbage values
begin //always begin
if (rst==1)
begin //rst 1 begin
//counter will be cleared
t_count=0;
sclk=0;
end //rst 1 end
else
begin //rst 0 begin
//counter counts normally
if(en==1)
begin
if(t_count<Nc)
begin
t_count=t_count+1;
sclk=sclk;
end
else
begin
t_count=0;
sclk=~sclk;
end
end
else
begin
//retains previous values
t_count=t_count;
sclk=sclk;
end
end //rst 0 end
end //always end
endmodule
Refresh counter code:
module refresh_counter(refreshclock,refreshcounter);
input refreshclock;
output reg[1:0] refreshcounter = 0;
always#(posedge refreshclock)
refreshcounter <= refreshcounter+1;
endmodule
Anode control code
module anode_control(refreshcounter,anode); //we want to make sure each anode is turned on based on each case value of the refresh counter
input[1:0] refreshcounter;
output reg[3:0] anode = 0;
always#(refreshcounter)
begin
case(refreshcounter)
2'b00: anode = 4'b1110; //digit 1 on (rightmost)
2'b01: anode = 4'b1101; //digit 2 on
2'b10: anode = 4'b1011; //digit 3 on
2'b11: anode = 4'b0111; //digit 4 on (leftmost)
endcase
end
endmodule
BCD control code:
module bcd_control(MUXED_digit, refreshcounter,digit1,digit2,digit3,digit4);
input[3:0] digit1; //rightmost digit (ones)
input[3:0] digit2; //tens
input[3:0] digit3; //hundreds
input[3:0] digit4; //leftmost digit(thousands)
input[3:0] refreshcounter; //because we are checking for both anode value and displayed value at the same time, and also to make sure both of them are in sync with each other
/*we are choosing which input digit to display when the corresponding anode is turned on. so we can say that the bcd control acts like a 4to1 mux with refreshcounter as select lines*/
output reg[3:0] MUXED_digit = 0;
always#(refreshcounter)
begin
case(refreshcounter)
2'd0: MUXED_digit = digit1; //digit 1 on (rightmost)
2'd1: MUXED_digit= digit2; //digit 2 on
2'd2: MUXED_digit = digit3; //digit 3 on
2'd3: MUXED_digit = digit4; //digit 4 on (leftmost)
endcase
end
endmodule
BCD to 7 segment code:
module bcd_7seg_case(bcd,S);
input [3:0] bcd;
//input cs;
output reg [6:0]S;
//circuit is sensitive to changes in inputs
always#(bcd)
begin
//if(~cs)
//S=0'b0000_000;
//else
//begin
case(bcd)
0: S = 7'b1111_110;
1: S = 7'b0110_000;
2: S = 7'b1101_101;
3: S = 7'b1111_001;
4: S = 7'b0110_011;
5: S = 7'b1011_011;
6: S = 7'b1011_111;
7: S = 7'b1110_000;
8: S = 7'b1111_111;
9: S = 7'b1111_011;
endcase
end
endmodule
I'm somewhat new to verilog. So this question might be very simple.
I'm trying to simulate an finite state machine using verilog.
Brief description:
There are three states: 0,1 & 2. By default, State is 0.
The state changes to 1 only if input is 01.
The state changes to 2 only if input is 10.
The state changes back to 0 only if input is 00.
The code is getting simulated successfully, but I.m getting no output. Please help me with the problem.
Code: (State.v)
module State(
input clk,
input reset,
input [3:0] in,
output [3:0] out,
output [3:0] state
);
wire clk,reset;
wire [3:0] in;
reg [3:0] out;
reg [3:0] state;
always #(posedge clk or posedge reset)
begin
if (reset == 1)
begin
state = 0;
end
else
begin
case (state)
0: if(in == 2'b01)
state = 1;
else
state = 0;
1: if(in == 2'b10)
state = 2;
else
state = 1;
2: if(in == 2'b00)
state = 0;
else
state = 2;
default: state = 0;
endcase
end
end
always #(*)
begin
case (state)
0: out = 2'b00;
1: out = 2'b01;
2: out = 2'b10;
default: out = 2'b00;
endcase
end
endmodule
Testbench: (StateTestBench.v)
module StateTestBench;
// Inputs
reg clk;
reg reset;
reg [3:0] in;
// Outputs
reg [3:0] out;
reg [3:0] state;
always
begin
#1 clk = !clk;
end
// Instantiate the Unit Under Test (UUT)
State uut (
.clk(clk),
.reset(reset),
.in(in),
.out(out),
.state(state)
);
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
#1 reset = 1;
#10 reset = 0;
#5 in = 2'b00;
#10 in = 2'b01;
#10 in = 2'b10;
end
endmodule
I guess you simulate state.v instead of StateTestBench.v. Because your testbench has a bug! Outputs out and state MUST be wires.
I want to write an eight bit ALU. I have written this code but when I simulate it, the output has x value,why did it happen? and I have another problem that I do not know how can I show 8 bit parameter in Modelsim simulation while I have just two value 0 or 1?
module eightBitAlu(clk, a, b,si,ci, opcode,outp);
input clk;
input [7:0] a, b;
input [2:0] opcode;
input si;
input ci;
output reg [7:0] outp;
always #(posedge clk)
begin
case (opcode)
3'b000: outp <= a - b;
3'b000 : outp <= a + b;
3'b001 : outp =0;
3'b010 : outp <= a & b;
3'b011 : outp <= a | b;
3'b100 : outp <= ~a;
endcase
end
endmodule
and this is my test module
module test_8bitAlu();
reg clk=0,a=3,b=1,si=0,ci=0,opcode=1;
eightBitAlu alu(clk, a, b,si,ci, opcode,outp);
initial begin
#200 clk=1;
#200 opcode=0;
#200 opcode=2;
#200 opcode=3;
#200 opcode=4;
#200;
end
endmodule
a and b are only 1 bit wide leaving the top 7 bits of your input ports un-driven.
reg clk=0,a=3,b=1,si=0,ci=0,opcode=1;
is equivalent to :
reg clk = 0;
reg a = 3;
reg b = 1;
reg si = 0;
reg ci = 0;
reg opcode = 1;
What you need is:
reg clk = 0;
reg [7:0] a = 3;
reg [7:0] b = 1;
reg si = 0;
reg ci = 0;
reg [2:0] opcode = 1;
wire [7:0] outp;
Further improvemnets would be to include the width on the integer assignment ie:
reg clk = 1'd0;
reg [7:0] a = 8'd3;
b for binary, d for decimal, o for octal and h for hexadecimal in width'formatValue
Note
outp if not defined will be an implicit 1 bit wire.
Your clock in the testharness also only has 1 positive edge. You may prefer to define your clock as:
initial begin
clk = 1'b0;
forever begin
#100 clk = ~clk;
end
end
A complete version of the above is demonstrated at EDAplayground.