I'm making a Multicycle CPU in Verilog that consists of a Datapath and a Control. The outputs of the control (state machine) are registers, but the connections between the datapath are wires. If a wire signal is supposed to be (in psuedo-code): wire = OR(wire coming from a mux, reg output from control), how do I do this? Can you OR a wire with a reg in Verilog? If not is there a better way to implement this? Can the control signal outputs be registers in the control module, but wires in the top module?
Update with picture for clarification:
Yes, you can or a wire and a reg output in Verilog.
Yes, each sub-module's outputs, which are essentially wires, can be directly or indirectly internally connected to a reg within the sub-module.
I think that is a fine way to do it.
Now, you can even declare the outputs of a module to be "reg", but that is just semantic sugar over declaring the output and reg separately. I like the explicit way better (i.e. q1_o and q1_reg).
module Submod(input clk_i, intput d_i, output q1_o, output reg q2_o);
reg q1_reg;
always #(posedge clk_i) begin
q1_reg <= d_i;
q2_o <= ~d_i;
end
assign q1_o = q1_reg;
endmodule
module Main(input clk_i, input [3:0]ext_i, output [1:0]ext_o)
wire mux, x1, x2;
Submod Submod_inst(clk_i, ext_i[0], x1, x2);
assign ext_o[0] = x1;
assign mux = ext_i[1] ? ext_i[2] : ext_i[3];
assign ext_o[1] = mux | x2; /* something like this */
endmodule
Related
I am kind of new to Verilog and was wondering how I can modify wires. I know that you cannot modify wires inside always blocks.
I've seen something like this where you can declare some regs and assign the wire to those regs (which you can then modify the reg to modify the wire?)
module something
#(parameter D_W = 8)
(
input wire clk,
input wire rst,
output wire valid,
output wire [D_W-1:0] data,
);
reg valid_rg = 0;
reg [D_W-1:0] data_rg = 0;
assign valid = valid_rg;
assign data = data_rg;
I was wondering how to do something like that for a wire like:
wire [7:0] wire_a [7:0];
Initially my guess would be to have something like this
reg [7:0] wire_a_rg [7:0];
assign wire_a[7:0] = wire_a_rg[7:0];
But I have a feeling it might be wrong. How could I approach this?
There's no need to use wires in SystemVerilog unless you need to model bi-directional buses, or any kind of circuitry with multiple drivers. You can write
module something
#(parameter D_W = 8)
(
input logic clk,
input logic rst,
output logic valid,
output logic [D_W-1:0] data,
);
And then you can make procedural assigmemnts to valid/data in an always block, or a continuous assign statement (but not both).
BTW, SystemVerilog prefers the use of logic keyword over synonym reg.
You should read my post about the difference between nets and variables.
I am trying to simulate a really basic memory model by having multiple memory blocks (initiations of a basic module) and tying the output of all those blocks to one wire. Is this the way to do this?
module memoryBlock(
input Enable,
output [7:0] dataOut,
input [7:0] dataIN
);
always #(*) begin
if(Enable == 1)
dataOut = dataIn;
end
endmodule;
The idea is that only one of these data blocks would be enabled at a time, and then I could pass whatever information was in the enabled block to the output wire. Here is how I would use it:
module testbench;
reg [7:0] exampleData1 = 8'b00000001;
reg [7:0] exampleData2 = 8'b11111111;
reg enable1 = 0;
reg enable2 = 1;
wire [7:0] outputForBoth;
memoryBlock mb1(enable1, outputForBoth, exampleData1);
memoryBlock mb2(enable2, outputForBoth, exampleData2);
endmodule;
When I have tried sample stuff like this before the output has just been 'zzzzzzzz'. My goal is to be able to have multiple memory blocks.. only enable one of them, and have that wire hold whatever data from that block. Is this the correct approach? Any help would be huge!
This way I only have one place I need to go to retrieve all of the output information. The other way I thought to do this was building a MUX of some sorts, and it just seems a lot more complicated that it needs to be!
You need tri-state outputs to do this. Tri-states drive a wire when enabled and are at high impedance state when not. But you need to make sure that you don't enable two modules at the same time.
module memoryBlock(
input enable,
inout [7:0] dataOut,
input [7:0] dataIN
);
assign dataOut = enable? dataIn : 8'bzzzzzzzz;
endmodule
Here i have a shifter but as of rite now it only works for up to 3 bits. I've been looking and i can't find out how to make it work for up to 8 bits.
module shifter(a,b,out);
input [7:0] a, b;
output [7:0] out;
wire [7:0] out1, out2, out3;
mux_8b_2to1 first(a[7:0], {a[3:0],a[7:4]}, b[2], out1);
mux_8b_2to1 second(out1[7:0], {out1[5:0],out1[7:6]}, b[1], out2);
mux_8b_2to1 third(out2[7:0], {out2[6:0],out2[7]}, b[0], out);
endmodule
What you have is a Barrel Shifter. Two ways to make it more generic are make it a functional model (still synthesis-able) or structural model with a generate block. Both approaches follow IEEE Std 1364-2001 (aka Verilog-2001).
The functional generic approach for a barrel shifter only needs a down-shifter. The general function is out = {in,in} >> (WIDTH-shift) where leftover bits can be ignored. To protect for double-roll (i.e. shift > WIDTH ), use the mod operator on the shift (WIDTH-(shift%WIDTH)).
module barrel_shifter_functional #( parameter CTRL=3, parameter WIDTH=CTRL**2 )
( input wire [WIDTH-1:0] in,
input wire [ CTRL-1:0] shift,
output wire [WIDTH-1:0] out );
assign out = {2{in}} >> (WIDTH-(shift%WIDTH));
endmodule
The structural generic approach for a barrel shifter needs a generate block. The for loop in the generate block will unravel at compile time, not run time like a for loop like in an always block. To keep it generic also have have the 2-to-1 mux have a parametrized width. FYI, you can use the generate block with functional code too, for example comment out the mux_2to1 instantiation and uncomment the assign statement below it. Learn more about the generate block by reading IEEE Std 1800-2012 ยง 27. Generate constructs.
module barrel_shifter_structeral #( parameter CTRL=3, parameter WIDTH=CTRL**2 )
( input wire [WIDTH-1:0] in,
input wire [ CTRL-1:0] shift,
output wire [WIDTH-1:0] out );
wire [WIDTH-1:0] tmp [CTRL:0];
assign tmp[CTRL] = in;
assign out = tmp[0];
genvar i;
generate
for (i = 0; i < CTRL; i = i + 1) begin : mux
mux_2to1 #(.WIDTH(WIDTH)) g(
.in0(tmp[i+1]),
.in1({tmp[i+1][WIDTH-(2**i)-1:0],tmp[i+1][WIDTH-1:WIDTH-(2**i)]}),
.sel(shift[i]),
.out(tmp[i]) );
// assign tmp[i] = shift[i] ? {tmp[i+1][WIDTH-(2**i)-1:0],tmp[i+1][WIDTH-1:WIDTH-(2**i)]} : tmp[i+1];
end : mux
endgenerate
endmodule
module mux_2to1 #( parameter WIDTH=8 )
( input wire [WIDTH-1:0] in0, in1,
input wire sel,
output wire [WIDTH-1:0] out );
assign out = sel ? in1 : in0;
endmodule
Both examples are functionally equivalent and synthesize provided CTRL is less than or equal to the ceiling of log2(WIDTH). Synthesis will likely give different results. The generate method will exclusively use 2-to-1 muxes while the pure functional method will depend on the quality of the optimizer.
Working example # http://www.edaplayground.com/s/6/500
I've used the >> and << operators to generate a synthetizable design using ISEWebPack, as this:
module shifter(
input wire [7:0] a,
input wire [7:0] b,
input wire leftright, // 0=shift right, 1=shift left
output reg [7:0] out
);
always #* begin
if (leftright==0)
out = a>>b;
else
out = a<<b;
end
endmodule
This way, the symthesis tool will know that you want to implement a shifter and can use its own macros to best synthetize it:
Synthesizing Unit <shifter>.
Related source file is "shifter.v".
Found 8-bit shifter logical right for signal <out$shift0002> created at line 30.
Found 8-bit shifter logical left for signal <out$shift0003> created at line 32.
I'm trying to use two switches to select the frequency I want to blink the led's at. My verilog code is as follows:
`timescale 1ns / 1ps
module clk_divider(
input clk,
input rst,
input [1:0] sw,
output led
);
reg n;
always#(sw[0],sw[1])
n = (27 - sw);
wire [n-1:0] din;
wire [n-1:0] clkdiv;
dff dff_inst0 (
.clk(clk),
.rst(rst),
.D(din[0]),
.Q(clkdiv[0])
);
genvar i;
generate
for (i = 1; i < n; i=i+1)
begin : dff_gen_label
dff dff_inst (
.clk(clkdiv[i-1]),
.rst(rst),
.D(din[i]),
.Q(clkdiv[i])
);
end
endgenerate;
assign din = ~clkdiv;
assign led = clkdiv[n-1];
endmodule
When I check for syntax, it says that "n is not constant." How can I avoid this error? To me, it seems that it should work. Any help would be appreciated!!!
With respect to wire [n-1:0] din; and wire [n-1:0] clkdiv;, you cannot have the width of a bus dependent on the value of an input.
A bus width is defined at synthesis time, it is the number of wires that exist in the physical device. Wires cannot appear or disappear based on the state of a module input or register.
You need to define these wires as having a fixed width, not a dynamic width. Maybe in some cases not all the wires will be used, but you must still define the bus as the maximum width that you will ever need. Similarly in the generate loop, you cannot change the number of flip-flops that are instantiated based on the value of n. You must instantiate as many flip flops as you will ever need, and then enable/disable some as needed.
Also you will hit this separate issue later, but your register n is only a single bit, so it cannot store any number other than 0 or 1. Make the register larger if you intend to hold greater values.
For the record, I'm a complete Verilog newbie. I'm writing a module that uses a few bidirectional buses.
inout wire [KEY_SIZE-1:0] prevKey;
inout wire [TAG_SIZE-1:0] prevTag;
inout wire [KEY_SIZE-1:0] nextKey;
inout wire [TAG_SIZE-1:0] nextTag;
I know how I read things off of the bus, but how do I write something onto it? If I use an assign statement to a reg, will the value of the reg get clobbered when new data comes onto the wire? Is dealing with an inout port worth the hassle, or should I just make an input and and output bus for each?
If I use an assign statement to a reg...
This statement doesn't really make sense, you don't do assignments to regs, you do assignments to wires.
Simple example of driving an inout wire:
inout wire bidir_wire;
reg drive_value;
reg drive_enable;
reg something;
assign bidir_wire = drive_enable ? drive_value : 1'bz;
always #(posedge clk) begin
drive_value <= ... ; //assign a drive value based on some criteria
drive_enable <= ...;
something <= bidir_wire; //do something with the input value
end