I am trying to add two 32 bits numbers using verilog.But I am getting many dont-care in the resut.
The 32 bit adder uses 4 8-bit adders.One 8 -bit adder uses one bit Full-Adder.FAdder makes use of 3 to 8 decoder.
Here is my code-
module Decoder(D,x,y,z);
input x,y,z;
output [0:7] D;
wire xn,yn,zn;
not n1(xn,x);
not n2(yn,y);
not n3(zn,z);
and a1(D[0],xn,yn,zn);
and a2(D[1],xn,yn,z);
and a3(D[2],xn,y,zn);
and a4(D[3],xn,y,z);
and a5(D[4],x,yn,zn);
and a6(D[5],x,yn,z);
and a7(D[6],x,y,zn);
and a8(D[7],x,y,z);
endmodule
module FAdder(S,C,x,y,z);
input x,y,z;
output S,C;
wire [0:7] D;
Decoder dec(D,x,y,z);
assign S= D[1] | D[2] | D[4] | D[7];
assign C= D[3] | D[5] | D[6] | D[7];
endmodule
module eightbitAdder(S,Carry,in1,in2,z);
input [7:0] in1;
input [7:0] in2;
input z;
output [7:0] S;
output Carry;
wire C[7:0];
assign z=0;
FAdder F1(S[0],C[0],in1[0],in2[0],z);
FAdder F2(S[1],C[1],in1[1],in2[1],C[0]);
FAdder F3(S[2],C[2],in1[2],in2[2],C[1]);
FAdder F4(S[3],C[3],in1[3],in2[3],C[2]);
FAdder F5(S[4],C[4],in1[4],in2[4],C[3]);
FAdder F6(S[5],C[5],in1[5],in2[5],C[4]);
FAdder F7(S[6],C[6],in1[6],in2[6],C[5]);
FAdder F8(S[7],C[7],in1[7],in2[7],C[6]);
assign Carry=C[7];
endmodule
module t32bitadder(S,Carry1,in1,in2);
input [31:0] in1,in2;
output [31:0] S;
output Carry1;
wire [3:0] C1;
wire initCarry;
assign initCarry=0;
eightbitAdder e1(S[7:0],C1[0],in1[7:0],in2[7:0],initCarry);
eightbitAdder e2(S[15:8],C1[1],in1[15:8],in2[15:8],C1[0]);
eightbitAdder e3(S[23:16],C1[2],in1[23:16],in2[23:16],C1[1]);
eightbitAdder e4(S[31:24],C1[3],in1[31:24],in2[31:24],C1[2]);
assign Carry1=C1[3];
endmodule
module testbench32bitAdder;
reg [31:0] in1,in2;
reg z;
wire [31:0] S;
wire C;
t32bitadder Al(S,C,in1,in2);
initial
$monitor(,$time,"in1=%b,in2=%b,S=%b,C=%b",in1,in2,S,C);
initial
begin
#0 in1=32'b00000001000000010000000110000001;in2=32'b00000001000000010000000110000001;
#4 in1=32'b11000001100000011000000100000001;in2=32'b11000001100000010000000100000001;
#4 in1=32'b00000001000000010000000100000001;in2=32'b10000001000000010000000100000001;
end
This is the result I am getting-
# 0in1=00000001000000010000000110000001,in2=00000001000000010000000110000001,S=0000001000000010000000xx00000010,C=0
# 4in1=11000001100000011000000100000001,in2=11000001100000010000000100000001,S=100000xx000000101000001000000010,C=1
# 8in1=00000001000000010000000100000001,in2=10000001000000010000000100000001,S=10000010000000100000001000000010,C=0
Notice the dont-care in the second output. This is because of the C1[2] which becomes X . Can anyone point out my mistake?
vipin is correct, the assign z=0; line in the eightbitAdder module is leading to the dont cares. In your test, the carry out of the first 8-bit adder is 1, it attempts to set the z input to the next 8-bit adder to 1, but this conflicts with the continuous assignment of z to 0, thus resulting in z = 1'bx. This dont care is propagated through the first FA and impacts the second as well, which results in the 2 dont cares in the 8th and 9th places of the result (where the first bit is the 0th place). The same thing is happening between your third and your final 8-bit adders in the second test. Your third test doesnt propagate a carry between 8-bit adders so no dont cares are generated.
Related
I am new to verilog, I was building a 32-bit adder using structural modelling. So I made a 1-bit full adder, then used that to construct a 4-bit adder, and that was used to create an 8- bit adder.
Everything works fine until the 4-bit adder but when I use the 4-bit adder as a function this error pops up.
module adder_1bit(Sum,CarryOut,A,B,CarryIn);
output Sum,CarryOut;
input A,B,CarryIn;
assign Sum = A^B^CarryIn;
assign CarryOut = (A&B) | (B&CarryIn) | (A&CarryIn);
endmodule
module adder_4bit(Sum,CarryOut,A,B,CarryIn);
output [3:0] Sum;
output CarryOut;
input [3:0] A,B;
input CarryIn;
wire w[2:0];
assign CarryIn = 1'b0;
adder_1bit add0(Sum[0],w[0],A[0],B[0],CarryIn);
adder_1bit add1(Sum[1],w[1],A[1],B[1],w[0]);
adder_1bit add2(Sum[2],w[2],A[2],B[2],w[1]);
adder_1bit add3(Sum[3],CarryOut,A[3],B[3],w[2]);
endmodule
module adder_8bit(Sum,CarryOut,A,B,CarryIn);
output [7:0] Sum;
output CarryOut;
input [7:0] A,B;
input CarryIn;
wire w;
assign CarryIn = 1'b0;
adder_4bit add4(Sum[3:0],w,A[3:0],B[3:0],CarryIn);
adder_4bit add5(Sum[7:4],CarryOut,A[7:4],B[7:4],w);
endmodule
When I run with the following testbench code I get MSB 4-bit get as don't care
module adder_test;
reg [7:0] A,B;
reg CarryIn;
wire [7:0] Sum;
wire CarryOut;
adder_8bit UUT (Sum,CarryOut,A,B,CarryIn);
initial
begin
A = 8'b00101011;
B = 8'b01010110;
CarryIn = 1'b0;
#10;
end
endmodule
Simulation Result
Your problem is in this statement: assign CarryIn = 1'b0;
The following happens:
module adder_4bit(Sum,CarryOut,A,B,CarryIn);
...
assign CarryIn = 1'b0;
In this case you have carryIn driven by two drivers:
the input port
the assign statement
Unless the value of the port is the same as your driver (1'b0) the resulting value of carryIn will always be 'x'. This interferes with all your results.
To fix the issue just move this statement to your test bench:
module adder_test;
...
wire CarryOut = 0;
`timescale 100ns/1ps
module CarryLAS_tb;
reg [7:0] a;
reg [7:0] b;
reg ci;
wire [7:0] sum;
wire of; //overflow
wire co;
integer i;
CarryLAS_8 CLA(a,b,ci,sum,co,of);
initial begin
a=0;
b=0;
ci=0;
end
initial begin // all possible cases
for(i=0; i<262144; i=i+1) // 2^18
#10 {a, b, ci} = i;
end
endmodule
module CarryLAS_8(a,b,ci,sum,co,of);
input [7:0] a,b;
input ci; // 0; Add 1: Subtract
output [7:0] sum;
output co;
output of;
wire[7:0] c;
wire[7:0] xb;
xor(xb[0],b[0],ci);
xor(xb[1],b[1],ci);
xor(xb[2],b[2],ci);
xor(xb[3],b[3],ci);
xor(xb[4],b[4],ci);
xor(xb[5],b[5],ci);
xor(xb[6],b[6],ci);
xor(xb[7],b[7],ci);
xor(of,c[7],c[6]);
xor(co,c[7],ci);
CarryLA_8 CLAS(a,xb,ci,sum,co);
endmodule
module CarryLA_8(a,b,ci,sum,co);
input [7:0] a,b;
input ci;
output [7:0] sum;
output co;
wire [7:0] sum;
wire cm,co;
CarryLA_4 CLA0(a[3:0],b[3:0],ci,sum[3:0],cm);
CarryLA_4 CLA1(a[7:4],b[7:4],cm,sum[7:4],cm);
endmodule
module CarryLA_4(a,b,ci,sum,co);
input [3:0] a,b;
input ci; // 0; Add 1: Subtract
output [3:0] sum;
output co;
wire[3:0] g,p,cout;
wire G0,P0;
wire[9:0] w;
and a0(g[0],a[0],b[0]);
and a1(g[1],a[1],b[1]);
and a2(g[2],a[2],b[2]);
and a3(g[3],a[3],b[3]);
xor x0(p[0],a[0],b[0]);
xor x1(p[1],a[1],b[1]);
xor x2(p[2],a[2],b[2]);
xor x3(p[3],a[3],b[3]);
and and0(w[0],p[0],ci);
or or0(cout[0],g[0],w[0]);
and and1(w[1],p[1],p[0],ci);
and and2(w[2],p[1],g[0]);
or or1(cout[1],g[1],w[2],w[1]);
and and3(w[3],p[2],p[1],p[0],ci);
and and4(w[4],p[2],p[1],g[0]);
and and5(w[5],p[2],g[1]);
or or2(cout[2],g[2],w[5],w[4],w[3]);
and and6(w[6],p[3],p[2],p[1],g[0]);
and and7(w[7],p[3],p[2],g[1]);
and and8(g[2],a[2],b[2]);
or or3(G0,g[3],w[8],w[7],w[6]);
and and9(P0,p[3],p[2],p[1],p[0]);
and and10(w[9],P0,ci);
or or4(cout[3],G0,w[9]);
and and11(co,cout[3],1);
xor xor0(sum[0],p[0],ci);
xor xor1(sum[1],p[1],cout[0]);
xor xor2(sum[2],p[2],cout[1]);
xor xor3(sum[3],p[3],cout[2]);
endmodule
This is my Verilog code. simulated well, but the result kinda sucks.
'sum' produces values with some Xs, and 'co', 'of'(overflow detection) are also Xs. I couldn't find out what the problem is. It might be about carry I think.
Could anyone help me with this?
Any help would be really appreciated.
Thanks in advance.
Captured waveform is attached
enter image description here
enter image description here
You have multiple drivers on wire [8:0] c. In your generate you have:
or o1 (c[i+1],g[i],q[i]);
and then you have the FullAdder instances that drive c:
FullAdder a0(a[0],b[0],ci,sum[0],c[0]);
I can't be certain that this is the reason that it won't simulate, but it certainly will make it not function correctly.
you should change "initial" part of your testbench like this:
initial
begin
assign ci =0;
assign a=8'b00000001;
assign b=8'b00000001;
#20
assign a=8'b00010010;
assign b=8'b00110111;
#20
assign a=8'b01011100;
assign b=8'b10010001;
#20
$finish;
and little wrong in module CarryLA_4 :
module CarryLA_4(a,b,ci,sum,co);
input [3:0] a,b;
input ci;
output [3:0] sum;
output co;
wire[3:0] g,p,cout;
wire G0,P0;
wire[9:0] w;
and a0(g[0],a[0],b[0]);
and a1(g[1],a[1],b[1]);
and a2(g[2],a[2],b[2]);
and a3(g[3],a[3],b[3]);
xor x0(p[0],a[0],b[0]);
xor x1(p[1],a[1],b[1]);
xor x2(p[2],a[2],b[2]);
xor x3(p[3],a[3],b[3]);
and and0(w[0],p[0],ci);
or or0(cout[0],g[0],w[0]);
and and1(w[1],p[1],p[0],ci);
and and2(w[2],p[1],g[0]);
or or1(cout[1],g[1],w[2],w[1]);
and and3(w[3],p[2],p[1],p[0],ci);
and and4(w[4],p[2],p[1],g[0]);
and and5(w[5],p[2],g[1]);
or or2(cout[2],g[2],w[5],w[4],w[3]);
and and6(w[6],p[3],p[2],p[1],g[0]);
and and7(w[7],p[3],p[2],g[1]);
and and8(w[8],p[3],p[2],p[1],p[0],ci);
and and9(w[9],p[3],g[2]);
or or3(cout[3],g[3],w[9],w[8],w[7],w[6]);
and and10(co,cout[3],1);
xor xor0(sum[0],p[0],ci);
xor xor1(sum[1],p[1],cout[0]);
xor xor2(sum[2],p[2],cout[1]);
xor xor3(sum[3],p[3],cout[2]);
endmodule
I am working on a ripple carry adder using structural verilog, which is supposed to take in two random inputs and calculate accordingly.
The general rca I created calculated correctly, but for some reason I get weird outputs when I add a for loop and use the $random to generate.
Could someone kindly explain where I'm going wrong? Below is my code:
module full_adder(x,y,z,v,cout);
parameter delay = 1;
input x,y,z; //input a, b and c
output v,cout; //sum and carry out
xor #delay x1(w1,x,y);
xor #delay x2(v,w1,z);
and #delay a1(w2,z,y);
and #delay a2(w3,z,x);
and #delay a3(w4,x,y);
or #delay o1(cout, w2,w3,w4);
endmodule
module four_bit_adder(a,b,s,cout,cin);//four_bit_adder
input [15:0] a,b; //input a, b
input cin; //carry in
output [15:0] s; //output s
output cout; //carry out
wire [15:0] c;
full_adder fa1(a[0],b[0],cin,s[0],c0);
full_adder fa2(a[1],b[1],c0,s[1],c1);
.
.
.
full_adder fa16(a[15],b[15],c14,s[15],cout);
endmodule
module testAdder(a,b,s,cout,cin);
input [15:0] s;
input cout;
output [15:0] a,b;
output cin;
reg [15:0] a,b;
reg cin;
integer i;
integer seed1=4;
integer seed2=5;
initial begin
for(i=0; i<5000; i=i+1) begin
a = $random(seed1);
b = $random(seed2);
$monitor("a=%d, b=%d, cin=%d, s=%d, cout=%d",a,b,cin,s,cout);
$display("a=%d, b=%d, cin=%d, s=%d, cout=%d",a,b,cin,s,cout);
end
end
endmodule
Here are two lines from the output that I get:
a=38893, b=58591, cin=x, s= z, cout=z
a=55136, b=58098, cin=x, s= z, cout=z
This is a combinational circuit, so the output changes instantaneously as the input changes. But, here you are apply all the inputs at same timestamp which should not be done since the full_adder module provides 1-timestamp delay. This may not cause problems in this module, but may cause issues while modelling sequential logic. Add a minimum of #10 delay between inputs.
Also, $monitor executes on each change in the signal list, so no need to use it in for loop. Just initialize $monitor in initial condition.
cin is also not driven from the testbench. Default value of reg is 'x and that of wire is 'z. Here, cin is reg, so the default value is displayed, that is 'x
One more thing, you must instantiate the design in your testbench. And connect respective ports. The outputs from testbench act as inputs to your design and vice-versa. This is just like you instantiate full_adder module in four_bit_adder module in design.
Consider testadder as top level module and instantiate design in it. No need of declaring ports as input and output in this module. Declare the design input ports as reg or wire(example: reg [15:0] a when a is design input port) and output ports as wire (example: wire [15:0] sum when sum is design input port).
Referring to your question:
The general rca I created calculated correctly, but for some reason I get weird outputs when I add a for loop and use the $random to generate.
Instead of using $random, use $urandom_range() to generate random numbers in some range. Using SystemVerilog constraints constructs can also help. Refer this link.
Using $urandom_range shall eliminate use of seed1 and seed2, it shall generate random values with some random machine seed.
Following is the module testadder with some of the changes required:
module testAdder();
wire [15:0] s;
wire cout;
// output [15:0] a,b;
// output cin;
reg [15:0] a,b;
reg cin;
integer i;
integer seed1=4;
integer seed2=5;
// Instantiate design here
four_bit_adder fa(a,b,s,cout,cin);
initial begin
// Monitor here, only single time
$monitor("a=%d, b=%d, cin=%d, s=%d, cout=%d",a,b,cin,s,cout);
for(i=0; i<5000; i=i+1) begin
// Drive inputs with some delays.
#10;
// URANDOM_RANGE for input generation in a range
a = $urandom_range(0,15);
b = $urandom_range(0,15);
// a = $random(seed1);
// b = $random(seed2);
// Drive cin randomly.
cin = $random;
$display("a=%d, b=%d, cin=%d, s=%d, cout=%d",a,b,cin,s,cout);
end
end
endmodule
For more information, have a look at sample testbench at this link.
I have written the simple code below for a magnitude comparator. The 6 bits of C give the values of A=B,A!=B,etc; However, i am getting the following error when i run the code. How can i fix the error?
c2q39.v:7: error: C['sd5] is not a valid l-value in testbench.m.
c2q39.v:3: : C['sd5] is declared here as wire.
My code is
module mag(A,B,C);
input [3:0] A,B;
output [5:0] C;
always # (A or B)
assign C[5]=(A==B);
assign C[4]=(A!=B);
assign C[3]=(A>B);
assign C[2]=(A<B);
assign C[1]=(A>=B);
assign C[0]=(A<=B);
endmodule
module testbench;
reg [3:0] A,B;
wire [5:0] C;
mag m(A,B,C);
initial
begin
A=4'b0000;B=4'b0000;
#10 A=4'b1000;
#10 B=4'b1001;
#10 A=4'b1000;
end
initial
$monitor("%0d %b %b %b",$time,A,B,C);
endmodule
It is not a good idea to use assign statement in always block ( for more details refer here ). So you can define your output C as reg and implement the following way:
module mag(A,B,C);
input [3:0] A,B;
output reg [5:0] C;
always # (A or B)
begin
C[5]=(A==B);
C[4]=(A!=B);
C[3]=(A>B);
C[2]=(A<B);
C[1]=(A>=B);
C[0]=(A<=B);
end
endmodule
The other way to implement is just use assign statements.
module mag(A,B,C);
input [3:0] A,B;
output [5:0] C;
//always # (A or B)
assign C[5]=(A==B);
assign C[4]=(A!=B);
assign C[3]=(A>B);
assign C[2]=(A<B);
assign C[1]=(A>=B);
assign C[0]=(A<=B);
endmodule
My design needs multiple multiplexers, all of them have two inputs and most are 32 bits wide. I started with designing the 32 bit, 2:1 multiplexer.
Now I need a 5 bit, 2:1 multiplexer and I want to reuse my 32 bit design. Connecting the inputs is easy (see code below), but I struggle to connect the output.
This is my code:
reg [4:0] a, b; // Inputs to the multiplexer.
reg select; // Select multiplexer output.
wire [4:0] result; // Output of the multiplexer.
multiplex32_2 mul({27'h0, a}, {27'h0, b}, select, result);
When I run the code through iverilog, I get a warning that says that the multiplexer expects a 32 bit output, but the connected bus is only 5 bit wide. The simulation shows the expected results, but I want to get rid of the warning.
Is there a way to tell iverilog to ignore the 27 unused bits of the multiplexer output or do I have to connect a 32 bit wide bus to the output of the multiplexer?
I don't know of a #pragma or something like that (similar to #pragma argsused from C) that can be used in Verilog.
Xilinx ISE, for example, has a feature called "message filtering", which allows the designer to silence specific warning messages. You find them once, select them, choose to ignore, and subsequent synthesis won't trigger those warnings.
Maybe you can design your multiplexer in a way you don't need to "waste" connections (not actually wasted though, as the synthesizer will prune unused connections from the netlist). A more elegant solution would be to use a parametrized module, and instantiate it with the required width. Something like this:
module mux #(parameter WIDTH=32) (
input wire [WIDTH-1:0] a,
input wire [WIDTH-1:0] b,
input wire sel,
output wire [WIDTH-1:0] o
);
assign o = (sel==1'b0)? a : b;
endmodule
This module has been tested with this simple test bench, which shows you how to instantiate a module with params:
module tb;
reg [31:0] a1,b1;
reg sel;
wire [31:0] o1;
reg [4:0] a2,b2;
wire [4:0] o2;
mux #(32) mux32 (a1,b1,sel,o1);
mux #(5) mux5 (a2,b2,sel,o2);
// Best way to instantiate them:
// mux #(.WIDTH(32)) mux32 (.a(a1),.b(b1),.sel(sel),o(o1));
// mux #(.WIDTH(5)) mux5 (.a(a2),.b(b2),.sel(sel),.o(o2));
initial begin
$dumpfile ("dump.vcd");
$dumpvars (1, tb);
a1 = 32'h01234567;
b1 = 32'h89ABCDEF;
a2 = 5'b11111;
b2 = 5'b00000;
repeat (4) begin
sel = 1'b0;
#10;
sel = 1'b1;
#10;
end
end
endmodule
You can test it yourself using this Eda Playground link:
http://www.edaplayground.com/x/Pkz
I think the problem relates to the output of the multiplexer which is still 5 bits wide. You can solve it by doing something like this:
reg [4:0] a, b; // Inputs to the multiplexer.
reg select; // Select multiplexer output.
wire [31:0] temp;
wire [4:0] result; // Output of the multiplexer.
multiplex32_2 mul({27'h0, a}, {27'h0, b}, select, temp);
assign result = temp[4:0];
This can be easily tested in http://www.edaplayground.com/ using the code below:
( I have re-used #mcleod_ideafix's code)
// Code your testbench here
// or browse Examples
module mux #(parameter WIDTH=32) (
input wire [WIDTH-1:0] a,
input wire [WIDTH-1:0] b,
input wire sel,
output wire [WIDTH-1:0] o
);
assign o = (sel==1'b0)? a : b;
endmodule
module tb;
reg [31:0] a,b;
wire [31:0] o;
wire [4:0] r;
reg sel;
initial begin
$dumpfile("dump.vcd"); $dumpvars;
a = 10; b = 20; sel = 1;
end
mux MM(a,b,sel,o);
assign r = o[4:0];
endmodule
Let me know if you are still getting a warning.