I am using this wire declaration in Verilog:
wire [23:15] myvar;
My code works and I have seen this coding style before, but I am not sure what is actually happening, I can only guess that a wire that is 9 bits wide is getting declared. Is that what is happening? I wanted to read more on this online, but i didn't know what this is called, so apologies for the simplistic question.
Verilog is a Hardware Descriptive Language(HDL). Whatever you write/declare, ultimately turns out to be a form of hardware.
Lets have a look at the image below:
Here, declaring wire [23:15] myvar; or wire [8:0] myvar; declares the same bunch of wires, nine bits wide. Its just the indexing part that differs. No matter you call it as a[0] (when a is wire [8:0] a) or a[15] (when a is wire [23:15] a). The coding part is different according to the ease for programmer, while synthesis part remains the same.
Also, note that in former case, myvar[15] is the least significant bit while latter has myvar[0] as the LSB. We can swap the declarations part, which shall swap the MSB-LSB too.
reg [7:0] reg1; // 8-bit vector with MSB=7 LSB=0
reg [0:7] reg2; // 8-bit vector with MSB=0 LSB=7
// ...
// ...
reg1 = 8'hF0; // reg1[7] = 1 and reg1[0] = 0 ultimately, reg1 = F0
reg2 = 8'hF0; // reg2[7] = 0 and reg2[0] = 1 ultimately, reg2 = F0
Lets take an example:
wire [23:15] myvar;
reg [23:15] reg2;
reg [31:0] reg3;
initial begin
$monitor("myvar = %0h myvar2 = %0h reg3 = %0h",myvar,myvar2,reg3);
reg3 = 32'h5ABC_FEDC;
// This will correctly assign values to reg2, since it is [23:15]
for(int i=16;i<20;i++)
begin
reg2[i] = myvar[i];
$display("1: reg2[%0d] = %0h myvar[%0d] = %0h",i,reg2[i],i,myvar[i]);
end
// While, this will not assign correctly,
// since reg2 does not have [5:0] indexes,neither does myvar
for(int i=0;i<5;i++)
begin
reg2[i] = myvar[i];
$display("2: reg2[%0d] = %0h myvar[%0d] = %0h",i,reg2[i],i,myvar[i]);
end
end
Another alternative is that your reg is [8:0] while wire is [23:0]. Here is all that matters, but just in the coding part. Note that in the first snippet below, values are assigned to reg1[4:0] and in the second snippet, it is in the range reg1[20:15].
reg [8:0] reg1;
wire [23:15] myvar;
// Correct, since LSB of myvar is at index position 15
for(int i=0;i<5;i++)
begin
reg1[i] = myvar[i+15];
$display("3 : reg1[%0d] = %0h myvar[%0d] = %0h",i,reg1[i],i,myvar[i+15]);
end
reg [31:0] reg1;
wire [23:15] myvar;
// reg1[19:15] is assigned here
for(int i=15;i<20;i++)
begin
reg1[i] = myvar[i];
$display("4 : reg1[%0d] = %0h myvar[%0d] = %0h",i,reg1[i],i,myvar[i]);
end
So, in the end, just some slicing differs while driving from the wire, no effect on the actual hardware. More information can be obtained from Verilog Syntax Details link.
You are correct that you are declaring a 9-bit wire. Many designs have different ideas about what the LSB and MSB values should be, which direction the index numbering should go in. It really doesn't matter what use for index values until you start referencing individual bit or slices.
Related
What I am trying to do in my mind is take 8 1-bit inputs and count the 1's. Then represent those 1's.
01010111 should output 0101 (There are five 1's from input)
module 8to4 (in,out,hold,clk,reset);
input [7:0] in; //1 bit inputs
reg [7:0] hold; //possible use for case statement
output [3:0] out; //Shows the count of bits
always #(clk)
begin
out = in[0] + in[1] + in[2] + in[3] + in[4] + in[5] + in[6] + in[7]; //Adds the inputs from testbench and outputs it
end
endmodule
Questions:
Is that the proper way to have 8 1-bit inputs? Or do I need to declare each variable as one bit ex: input A,B,C,D,E,F,G,H;
If my above code is close to being correct, is that the proper way to get out to display the count of 1's? Would I need a case statement?
I'm really new to verilog, so I don't even want to think about a test bench yet.
The way you wrote it is probably the better way of writing it because it makes it easier to parameterize the number of bits. But technically, you have one 8-bit input.
module 8to4 #(parameter WIDTH=8) (input [WIDTH-1:0] in,
output reg [3:0] out,hold,
input clk,reset);
reg [WIDTH-1:0] temp;
integer ii;
always #(clk)
begin
temp = 0;
for(ii=0; ii<WIDTH; i = i + 1)
temp = temp + in[ii];
out <= temp;
end
endmodule
Logically the code is proper.
However you can improve it like the following.
Make out as a reg, because you are using it in a procedural assignment.
Usage of reset. Ideally any code should have reset state, which is missing in your code.
Declare the direction (input/output) for hold, clk & reset port, which is currently not specified.
As dave mentioned, you can use parameters for your code.
So I have been following a guide provided by EmbeddedMicro on producing a simple 16 bit CPU using their HDL Lucid. My goal is to convert this over to Verilog in Quartus II. The problem I am having is trying to store the bits allocated for the destination of my data into a specific range of bits inside the designated register. The second problem I am having is using a global Constant as one of case values. I was able to get around this by just replacing with the constant value. I have already added the include file into the project settings. I am still new to Verilog so their might be an abundant of bad code.
The error recieved is on line 57
shift_r.D[DEST] = DIN; //supposed to be storing the data coming in into register
Error Readout: Verilog Syntax Error, near text: "=". Check for and fix any syntax errors that appear immediately before or at the specified keyword
`include "CPU_8/my_incl.vh"
module CPU(CLK,RST,WRITE,READ,ADDRESS,DOUT,DIN);
input RST,CLK;
input [0:7] DIN; //DATA in
output reg [0:7] ADDRESS;
output reg [0:7] DOUT; //DATA OUT
output reg WRITE,READ;
reg [0:15] INST;
//I am not sure if i set up the array for my registers correctly either
shiftreg shift_r[0:15] (RST, CLK, D, Q); //initialize shift_r and create array of 16 registers.
//Implicit net is created for the D and Q above when generating block file
instRom_16 instRoms(ADDRESS, INST); //intialize InstRom_16 module
reg [0:3]OP; // opcode
reg [0:3]ARG1; // first arg
reg [0:3]ARG2; // second arg
reg [0:3]DEST; // destination arg
reg [0:7]CONSTANT; //Constant
always#(posedge CLK)
begin
WRITE = 0; // don't write
READ = 0; // don't read
ADDRESS = 8'b0; // don't care
DOUT = 8'b0; // don't care
instRoms.ADDRESS = shift_r.D[0]; //Set shift_reg to be program counter
shift_r.D = shift_r.Q[0] + 1; //increment program counter.
OP = instRoms.INST[15:12]; // opcode first 4 bits
DEST = instRoms.INST[11:8]; // destination one 4 bits
ARG1 = instRoms.INST[7:4]; // argument2 is next 4 bits
ARG2 = instRoms.INST[3:0]; // ARGUMENT2 is last 4 bits
CONSTANT = instRoms.INST[7:0];
//PERFORM OPERATIONS
case (OP)
4'd1: //tried to use `LOAD but that wouldn't point to the value in my include file
READ = 1; // request a read
//line that is failing
shift_r.D[DEST] = DIN; //supposed to be storing the data coming in into register
//4'd2:
endcase
end
endmodule
This is my include file
`ifndef _my_incl_vh_
`define _my_incl_vh_
`define NOP = 4'd0; // 0 filled
`define LOAD = 4'd1; // load
`endif
You made a little mistake:
shiftreg shift_r[0:15] (RST, CLK, D, Q);
Instantiates an array of shift_r, each instance of which has a RST, CLK, D and Q.
So shift_r.D[DEST] should become shift_r[DEST].D and shift_r.Q[0] should become shift_r[0].Q.
For shift_r.D, is guess you want a 0:15 vector. You will need to assign all 16 bits to an intermediate wire of 15 bits using e.g. a for loop.
I write Verilog program to simulate memory transfer to Temp , but i got a lot of errors, help please.
wire [64:0] temp,mem [0:256];
wire [15:0] w0, w1, w2, w3;
wire [7:0] block_nr;
integer i ;
for ( i=0; i <3; i = i + 1) begin
temp = mem [i];
data_mem [i] = {block_nr, w0,w1, w2, w3 };
block_nr = block_nr +1;
end
5There are many errors in your code. Here are some:
a) Instead of this:
wire [64:0] temp,mem [0:256];
perhaps you mean this?
wire [64:0] mem [0:256]; // this might be a reg, too, one cannot tell from your code snippet
reg [64:0] temp;
i) I don't think you meant temp to be a 65x257 array as well as mem? And did you mean "64"? Or "63"? Or (see below) "71"? And did you mean "256"? Or "255"?
ii) You cannot assign to a wire from inside a procedural block.
b) This needs to be a reg, too, because (again) you cannot assign to a wire from inside a procedural block.
reg [7:0] block_nr;
c) This code needs to go inside a procedural block, either initial or always. Which depends on your design intent - I cannot tell this from your snippet of code. Let's assume initial:
initial begin
for ( i=0; i <3; i = i + 1) begin
temp = mem [i];
data_mem [i] = {block_nr, w0,w1, w2, w3 }; // what is "data_mem"? Did you mean "mem"?
// if you did mean "mem", did you notice that "{block_nr, w0,w1, w2, w3 }" is 72 bits wide?
block_nr = block_nr +1;
end
end
If this is intended to be synthesised, the you cannot use initial. If you do intend to synthesise this, you are a long way from a working solution.
I must emphasise, however, that these are merely suggestions. It is not possible to completely correct errors in code whose design intent is not known.
wire [9:0] data_reg;
reg [3:0] Reverse_Count = 8; //This register is derived in logic and I need to use it in following logic in order to reverse the bit position.
assign data_reg[9:0] = 10'h88; // Data Register
genvar i;
for (i=0; i< Reverse_Count; i=i+1)
assign IReg_swiz[i] = IReg[Reverse_Count - 1 -i];
This is generating syntax error. May I know how to do this in verilog
If you'd have Reverse_Count as constant, your task boils down to just wire mix-up, which is essentially free in HDL.
In your case, the task can be nicely reduced to first mirroring wide data and then shifting by Reverse_Count to get LBS bit on its position, which itself is done just by a row of N-to-1 multiplexers.
integer i;
reg [9:0] reversed;
wire [9:0] result;
// mirror bits in wide 10-bit value
always #*
for(i=0;i<10;i=i+1)
reversed[i] = data_reg[9-i];
// settle LSB on its place
assign result = reversed>>(10-Reverse_Count);
Reverse_Count is not a constant, ie it is not a parameter or localparam.
This means that the generate statement you would be creating and destroying hardware as required, this is not allowed in verilog as it would not be possible in hardware.
The Bus that your reversing should have a fixed width at compile time, it should be possible to declare Reverse_Count as a parameter.
Since the value of Reverse_Count dunamic, you cannot use a generate statement. You can use an always block with for-loop. To be synthesizable, the for-loop needs able to static unroll. To decide which bits reverse, use an if condition to compare the indexing value and Reverse_Count
Example:
parameter MAX = 10;
reg [MAX-1:0] IReg_swiz;
integer i;
always #* begin
for (i=0; i < MAX ; i=i+1) begin
if (i < Reverse_Count) begin
IReg_swiz[i] = IReg[Reverse_Count - 1 -i];
end
else begin
// All bits need to be assigned or complex latching logic will be inferred.
IReg_swiz[i] = IReg[i]; // Other values okay depending on your requirements.
end
end
end
I am trying to count the number of ones in a 4-bit binary number in Verilog, but my output is unexpected. I've tried several approaches; this is the one I think should work, but it doesn't.
module ones(one,in);
input [3:0]in;
output [1:0]one;
assign one = 2'b00;
assign one = one+in[3]+in[2]+in[1]+in[0] ;
endmodule
First, you can't assign the variable twice.
Second, your range is off, 2 bits can only go from 0 to 3. You need a 3 bit output to count up to 4.
This is more like what you need:
module ones(
output wire [2:0] one,
input wire [3:0] in
);
assign one = in[3]+in[2]+in[1]+in[0] ;
endmodule
$countones can be used for this purpose (refer to IEEE Std 1800-2012, 20.9 Bit vector system functions):
module tb;
reg [3:0] in;
wire [2:0] one = $countones(in);
initial begin
$monitor("in=%b one=%d", in, one);
#1 in = 4'b0000;
#1 in = 4'b0001;
#1 in = 4'b1101;
end
endmodule
Output:
in=xxxx one=0
in=0000 one=0
in=0001 one=1
in=1101 one=3