I've designed a unit for my homework here,
module homework1(a, b, sel, y);
input signed [7:0] a, b;
input [1:0] sel;
output reg signed [7:0] y;
always #(a or b or sel) begin
case (sel)
2'b00: y = a + b;
2'b01: y = a - b;
2'b10: y = (a > b) ? a : b;
2'b11: y = (a > b) ? b : a;
endcase
end
endmodule
I've designed a pretty simple testbench file to run with Modelsim here,
module testbench();
reg signed [7:0] a, b;
reg [1:0] sel;
wire signed [7:0] y;
homework1 target(a, b, sel, y);
initial begin
$display("Hello!");
$monitor($time, "a = %d, b = %d, sel = %b, y = %d", a, b, sel, y);
#10 sel = 0; a = 32; b = 25;
#10 a = 46; b = 0;
#10 a = 18; b = 52;
#10 a = 37; b = 37;
#10 a = 37; b = 37;
#10 $stop;
end
endmodule
I used Modelsim to run the test bench, and while the waveform came out as expected, but not the text output. Any ideas?
It seems to work in older version of Modelsim. I'm using 10.3d now. Any settings that might cause this?
Try running your simulations with the -displaymsgmode=both optional argument. The messages may be hidden from your transcript because displaymsgmode is set to wlf.
See the modelsim manual on page 581 for more information.
Related
I'm trying to build an 8-bit multiplier in Verilog, but I keep running in to this weird error when I go to simulate my module's test bench. It says:
Too many port connections. Expected 8, found 9
This doesn't really make any sense seeing as how both the module AND the test bench have 9 variables listed. Any help will be much appreciated!
Multiplier Module
module my8bitmultiplier (output [15:0] O, output Done, Cout, input [7:0] A, B, input Load, Clk, Reset, Cin);
reg Done;
reg [1:0] state;
reg [7:0] A_reg, B_reg;
reg [15:0] A_temp, B_temp, O_temp, O_reg;
my16bitadder Adding(O_temp, Cout,A_temp,B_temp, Cin);
always#(posedge Clk)
begin
if(Reset) assign state = {2'b00};
case(state)
0:
if(Load)
begin
A_reg = A;
B_reg = B;
O_reg = A_reg;
state = 1;
end
1:
begin
A_temp = A_reg;
B_temp = O_reg;
B_reg = B_reg - 1;
state = 2;
end
2:
begin
O_reg = O_temp;
if(B_temp)
begin
state = 1;
end
else
begin
state = 3;
Done = 1'b1;
end
end
3:
begin
Done = 1'b0;
state = 0;
end
endcase
end
endmodule
Testbench
module my8bitmultiplier_tb;
reg Load, Clk, Reset, Cin;
reg [7:0] A, B;
wire [15:0] O;
wire Done, Cout;
my8bitmultiplier dut(O, Done, Cout, A, B, Load, Clk, Reset, Cin);
always #5 Clk = ~Clk;
initial
begin
A = 8'b10;
B = 8'b10;
Load = 1;
Cin = 0;
#10 Load = 0;
#3000 A = 8'd100;
#3000 B = 8'd100;
#3000 Load = 1;
#3010 Load = 0;
#6000 A = 8'd150;
#6000 B = 8'd150;
#6000 Load = 1;
#6000 Load = 0;
begin
$display ($time,"A= %d B= %d O=%d ", A, B, O);
end
#10000 $finish;
end
endmodule
When I run you code on another simulator, I get a more helpful warning message:
reg Done;
|
xmvlog: *W,ILLPDX : Multiple declarations for a port not allowed in module with ANSI list of port declarations (port 'Done') [12.3.4(IEEE-2001)].
The warning goes away when I delete this line:
reg Done;
and change:
module my8bitmultiplier (output [15:0] O, output Done, Cout, input [7:0] A, B, input Load, Clk, Reset, Cin);
to:
module my8bitmultiplier (output [15:0] O, output reg Done, Cout, input [7:0] A, B, input Load, Clk, Reset, Cin);
Perhaps that solves your problem on modelsim. You can also try your code on different simulators on edaplayground. You will sometimes get more helpful messages.
I'm attempting to run a behavioral simulation on my Verilog code in Vivado. However, after the simulation runs, instead of getting outputs, they are shown as red lines with XX, which I believe means they are undefined.
I've attempted to change the timescale at the top of the Verilog files, as shown in Xilinx forum post, but this did not fix my issue.
Here is my Verilog program:
module ctrl(
input clk,
input [5:0] A,
input [5:0] B,
input [3:0] C,
output reg [6:0] led
);
always #(posedge clk)
begin
case(C)
4'b0000:
//A + B
led <= A + B;
4'b0001:
//A - B
led <= A - B;
4'b0010:
//A++
led <= A + 1'b1;
4'b0011:
//A--
led <= A - 1'b1;
4'b0100:
//B++
led <= B + 1'b1;
4'b0101:
//B--
led <= B - 1'b1;
4'b0110:
//A & B
led = (A & B);
4'b0111:
//A | B
led = (A | B);
4'b1000:
//A ^ B
led = (A ^ B);
4'b1001:
//~A
led = {1'b0,~A[5:0]
4'b1010:
//~B
led = {1'b0,~B[5:0]};
4'b1011:
//A << B
led = A << B;
4'b1100:
//B << A
led = B << A;
4'b1101:
//Light LED[0] if A > B
if(A > B)
led = 7'b0000001;
else
led = 7'b0000000;
4'b1110:
//Light LED[0] if A < B
if(A < B)
led = 7'b00000001;
else
led = 7'b0000000;
4'b1111:
//Light LED[0] if A=B
if(A == B)
led = 7'b0000001;
else
led = 7'b0000000;
default:
//Unimplemented opcode
led <= 7'b1111111;
endcase
end
endmodule
The testbench
module ctrl_testbench();
reg[5:0] A;
reg[5:0] B;
reg[3:0] C;
wire[6:0] led;
ctrl dut (
.A(A),
.B(B),
.C(C),
.led(led)
);
initial begin
A = 6'b000001;
B = 6'b000001;
C = 4'b0000;
#100;
A = 6'b000000;
B = 6'b000000;
C = 4'b0000;
#100;
A = 6'b000010;
B = 6'b000010;
C = 4'b0001;
end
endmodule
The timing diagram then gives this after the behavioral simulation is run. As you can see A-C (The inputs) are populated correctly, however LED (the output) is red and shows XX.
I'm trying to show the actual outputs.
You need to create a clock signal and drive the clk input of your DUT:
module ctrl_testbench();
reg[5:0] A;
reg[5:0] B;
reg[3:0] C;
wire[6:0] led;
reg clk;
initial begin
clk = 0;
forever #5 clk = ~clk;
end
ctrl dut (
.clk(clk),
.A(A),
.B(B),
.C(C),
.led(led)
);
initial begin
A = 6'b000001;
B = 6'b000001;
C = 4'b0000;
#100;
A = 6'b000000;
B = 6'b000000;
C = 4'b0000;
#100;
A = 6'b000010;
B = 6'b000010;
C = 4'b0001;
$finish;
end
endmodule
It was convenient for me to create 2 initial blocks. The first never ends due to forever, and the second is necessary to end the simulation with $finish. It is common to separate out distinct functionality using multiple initial blocks.
I've written two different Verilog snippets for combinational and sequential multiplication, which I post below. When I simulate either of the multiplications the multiplier, denoted mult_A and multiplicand, denoted mult_B show their bit-string values, but the resulting product, denoted R shows all Xs. Help in showing the codes multiplication result R would be greatly appreciated.
Combinational
module com_multiplication(mult_A, mult_B, R);
input [15:0] mult_A, mult_B;
output R;
reg [31:0] R;
integer k;
always#(mult_A, mult_B)
begin
R = 0;
for(k = 0; k < 16; k = k + 1)
if(mult_A[k] == 1'b1) R = R + (mult_B << 1);
end
endmodule
Serial
module ser_multiplication(mult_A, mult_B, clk, start, R, finish);
input [15:0] mult_A, mult_B;
input clk, start;
output R, finish;
reg [31:0] R;
reg [15:0] mult_A_duplicate;
reg [31:0] mult_B_duplicate;
reg [4:0] p;
wire finish = !p;
initial p = 0;
always#(posedge clk)
if (finish && start) begin
p = 16;
R = 0;
mult_B_duplicate = {16'd0, mult_B};
mult_A_duplicate = mult_A;
end else if (p) begin
if (mult_A_duplicate[0] == 1'b1) R = R + mult_B_duplicate;
mult_A_duplicate = mult_A_duplicate >> 1;
mult_B_duplicate = mult_B_duplicate << 1;
p = p - 1;
end
endmodule
Testbench
For now the serial part is commented out.
module multiplication_tb;
reg clk, start, finish;
reg [15:0] mult_A, mult_B;
reg [31:0] R;
com_multiplication U0 (
.mult_A (mult_A),
.mult_B (mult_B),
.R (R)
);
/*ser_multiplication U1 (
.clk (clk),
.start (start),
.finish (finish),
.mult_A (mult_A),
.mult_B (mult_B),
.R (R)
); */
initial
begin
$display("time\t clk start finish");
$monitor ("%g\t %b %b %b %b %b %b", $time, clk, start, finish, mult_A,
mult_B, R);
#100 clk = 0;
mult_A =0;
mult_B = 0;
#10 mult_A = 2;
mult_B = 3;
#20 mult_B=2;
#10 mult_B=5;
#100 $finish;
end
always
#5 clk = !clk;
endmodule
I just glanced at your code but it looks like your clock is not toggling. Simple way to make a forever toggling clock is:
initial
begin
clk = 1'b0;
forever
#50 clk = ~clk;
end
I want it to show the output of the flip flop but instead it lists the output as 'Z'. How can I get it to do this?
Code:
module d_flip_flop_edge_triggered(Q, Qn, C, D);
output Q;
output Qn;
input C;
input D;
wire Q;
wire Qn;
wire Cn;
wire Cnn;
wire DQ;
wire DQn;
not(Cn, C);
not(Cnn, Cn);
endmodule
This is the test bench - I think the problem lies here.
TestBench:
module ffTB;
// Inputs
reg C;
reg D;
// Outputs
wire Q;
wire Qn;
// Instantiate the Unit Under Test (UUT)
d_flip_flop_edge_triggered uut (
.Q(Q),
.Qn(Qn),
.C(C),
.D(D)
);
initial begin
// Initialize Inputs
C = 0;
D = 0;
// Wait 100 ns for global reset to finish
#100;
C = 1;
D = 1;
#100;
C = 0;
#100;
C = 1;
#100;
C = 0;
#100;
C = 1;
#100;
C = 0;
end
endmodule
Thank you my grade depends on it!
Your model for the flip-flop is completely wrong. (Sorry, but it's true.) With the exception of the input C, none of the inputs or outputs are connected to anything! As a result, the testbench shows that the outputs are floating, which is denoted by the value Z.
Your D flip-flop RTL,
module d_flip_flop_edge_triggered( output reg Q,
output wire Qn,
input wire clk,
input wire rst_n,
input wire D
);
always # (posedge clk or negedge rst_n)
begin
if (~rst_n)
begin
Q <= 1'b0;
end
else
begin
Q <= D;
end
end
assign Qn = ~Q;
endmodul
And Testbench,
module ffTB;
reg clk;
reg rst_n;
reg D;
wire Q, Qn;
d_flip_flop_edge_triggered d_flip_flop_edge_triggered_inst (Q, Qn, clk, rst_n, D);
initial
begin
clk = 1'b0;
rst_n = 1'b0;
D = 1'b0;
#10 rst_n = 1'b1;
#600 $finish;
end
always clk = #5 ~clk;
initial
begin
repeat (100)
begin
D = $random;
#5;
end
end
endmodule
with simulation,
I want to write an eight bit ALU. I have written this code but when I simulate it, the output has x value,why did it happen? and I have another problem that I do not know how can I show 8 bit parameter in Modelsim simulation while I have just two value 0 or 1?
module eightBitAlu(clk, a, b,si,ci, opcode,outp);
input clk;
input [7:0] a, b;
input [2:0] opcode;
input si;
input ci;
output reg [7:0] outp;
always #(posedge clk)
begin
case (opcode)
3'b000: outp <= a - b;
3'b000 : outp <= a + b;
3'b001 : outp =0;
3'b010 : outp <= a & b;
3'b011 : outp <= a | b;
3'b100 : outp <= ~a;
endcase
end
endmodule
and this is my test module
module test_8bitAlu();
reg clk=0,a=3,b=1,si=0,ci=0,opcode=1;
eightBitAlu alu(clk, a, b,si,ci, opcode,outp);
initial begin
#200 clk=1;
#200 opcode=0;
#200 opcode=2;
#200 opcode=3;
#200 opcode=4;
#200;
end
endmodule
a and b are only 1 bit wide leaving the top 7 bits of your input ports un-driven.
reg clk=0,a=3,b=1,si=0,ci=0,opcode=1;
is equivalent to :
reg clk = 0;
reg a = 3;
reg b = 1;
reg si = 0;
reg ci = 0;
reg opcode = 1;
What you need is:
reg clk = 0;
reg [7:0] a = 3;
reg [7:0] b = 1;
reg si = 0;
reg ci = 0;
reg [2:0] opcode = 1;
wire [7:0] outp;
Further improvemnets would be to include the width on the integer assignment ie:
reg clk = 1'd0;
reg [7:0] a = 8'd3;
b for binary, d for decimal, o for octal and h for hexadecimal in width'formatValue
Note
outp if not defined will be an implicit 1 bit wire.
Your clock in the testharness also only has 1 positive edge. You may prefer to define your clock as:
initial begin
clk = 1'b0;
forever begin
#100 clk = ~clk;
end
end
A complete version of the above is demonstrated at EDAplayground.