Can someone explain to me what I am doing wrong. I don't know if I just don't understand the concept or what. I have looked at two solid examples, both of which provide thorough code but maybe I am wiring things wrong or something.
1st - I have created an file called Adder and below is my code. This works completely fine, I have created/ran a test bench file with this so I know this does exactly what is intended. However, am I supposed to somehow connect my FullAdder file or the test bench for the FullAdder file to the Adder file? Are these completely separate files and are never connected?
module Adder (a,b,ci,co,s);
input a,b,ci;
output co,s;
assign s=a^b^ci;
assign co=(a&b)|(a&ci)|(b&ci);
endmodule
2nd - Below is my code for the FullAdder file. I am not sure if this is correct but let me know where I can make possible changes. I assume the test bench I create will be linked to this FullAdder file? The syntax for this file checks out alright, so maybe it is the test bench that is causing problems for me...
module FullAdder(a,b,ci,s);
input [3:0] a,b;
input ci;
output [3:0] s;
wire [2:0] co; // Is the wire correct here? I created this off something I saw.
Adder ADD1(a[0],b[0],ci,s[0],co[0]);
Adder ADD2(a[1],b[1],co[0],s[1],co[1]);
Adder ADD3(a[2],b[2],co[1],s[2],co[2]);
Adder ADD4(a[3],b[3],co[2],s[3],s[4]);
endmodule
3rd - I don't understand the test bench and wiring everything all together. I have looked at these two links which have two different ways of doing this.
Link 1 Link 2. I have tried to replicate link 2, but can't seem to get it working. Help?
Adder ADD4(a[3],b[3],carry[2],s[3],s[4]);
This instantiation assumes that s is a vector with an element in position 4, but your definition of s is [3:0] so 4 is not a valid position. Change it to
output [4:0] s;
It's desiderabel to use the Verilog 2001 module definition style (resembles ANSI C). Your module would be like this:
module FullAdder (
input wire [3:0] a,
input wire [3:0] b,
input wire ci,
output wire [4:0] s
);
wire [2:0] co;
Adder ADD1(a[0],b[0],ci,s[0],co[0]);
Adder ADD2(a[1],b[1],co[0],s[1],co[1]);
Adder ADD3(a[2],b[2],co[1],s[2],co[2]);
Adder ADD4(a[3],b[3],co[2],s[3],s[4]);
endmodule
Regarding your test bench (link 2) you mispelled some names: the name of 1-bit address is called "adder", not "Adder". Change either the definition or the instance name. The name of the ports are a,b,cin and s, not p,q,ci and r. These last are the signals (wires) you will connect to your ports.
As this adder has a limited set of inputs, I'd suggest to do an exhaustive test bench. So instead of probing two sample values for a,b and cin, try all the posibilities, and check that the result is the expected one. Something like this:
// Code your testbench here
module test_bench;
// Inputs
reg [3:0] p;
reg [3:0] q;
reg ci;
// Outputs
wire [4:0] r;
// Instantiate the Unit Under Test (UUT)
FullAdder uut (
.a(p),
.b(q),
.ci(ci),
.s(r)
);
initial begin
ci = 1'b0;
repeat (2) begin
p = 4'b0000;
repeat (16) begin
q = 4'b0000;
repeat (16) begin
#10;
$display ("%b + %b + %b = %b", p, q, ci, r);
if (r != (p+q+ci)) begin
$display ("ERROR!. Expected %b", p+q+ci);
$finish;
end
#10;
q = q + 1;
end
#10;
p = p + 1;
end
#10;
ci = !ci;
end
$display ("EVERYTHING OK!");
$finish;
end
endmodule
See http://www.edaplayground.com/x/HR5
Related
I am new to verilog, I was building a 32-bit adder using structural modelling. So I made a 1-bit full adder, then used that to construct a 4-bit adder, and that was used to create an 8- bit adder.
Everything works fine until the 4-bit adder but when I use the 4-bit adder as a function this error pops up.
module adder_1bit(Sum,CarryOut,A,B,CarryIn);
output Sum,CarryOut;
input A,B,CarryIn;
assign Sum = A^B^CarryIn;
assign CarryOut = (A&B) | (B&CarryIn) | (A&CarryIn);
endmodule
module adder_4bit(Sum,CarryOut,A,B,CarryIn);
output [3:0] Sum;
output CarryOut;
input [3:0] A,B;
input CarryIn;
wire w[2:0];
assign CarryIn = 1'b0;
adder_1bit add0(Sum[0],w[0],A[0],B[0],CarryIn);
adder_1bit add1(Sum[1],w[1],A[1],B[1],w[0]);
adder_1bit add2(Sum[2],w[2],A[2],B[2],w[1]);
adder_1bit add3(Sum[3],CarryOut,A[3],B[3],w[2]);
endmodule
module adder_8bit(Sum,CarryOut,A,B,CarryIn);
output [7:0] Sum;
output CarryOut;
input [7:0] A,B;
input CarryIn;
wire w;
assign CarryIn = 1'b0;
adder_4bit add4(Sum[3:0],w,A[3:0],B[3:0],CarryIn);
adder_4bit add5(Sum[7:4],CarryOut,A[7:4],B[7:4],w);
endmodule
When I run with the following testbench code I get MSB 4-bit get as don't care
module adder_test;
reg [7:0] A,B;
reg CarryIn;
wire [7:0] Sum;
wire CarryOut;
adder_8bit UUT (Sum,CarryOut,A,B,CarryIn);
initial
begin
A = 8'b00101011;
B = 8'b01010110;
CarryIn = 1'b0;
#10;
end
endmodule
Simulation Result
Your problem is in this statement: assign CarryIn = 1'b0;
The following happens:
module adder_4bit(Sum,CarryOut,A,B,CarryIn);
...
assign CarryIn = 1'b0;
In this case you have carryIn driven by two drivers:
the input port
the assign statement
Unless the value of the port is the same as your driver (1'b0) the resulting value of carryIn will always be 'x'. This interferes with all your results.
To fix the issue just move this statement to your test bench:
module adder_test;
...
wire CarryOut = 0;
I am trying to implement a 4 bit right shifter using gate level but i got unknown result for some reason, my mux work ok but when i try testbench for my shifter it give back something like this:
a=0010 b=01 c=0000
a=1111 b=01 c=00xx
Please help!!!! Thank you very much
module mux2(a,b,sel,c);
output c;
input a,b,sel;
wire net0,net1,net2;
not m1(net0,sel);
and m2(net1,a,net0);
and m3(net2,b,sel);
or m4(c,net1,net2);
endmodule
module mux4(a,sel,c);
output c;
input [1:0]sel;
input[3:0]a;
wire mux_1,mux_2;
mux2 m1(a[3],a[2],sel[0],mux_1);
mux2 m2(a[1],a[0],sel[0],mux_2);
mux2 m3(mux_1,mux_2,sel[1],c);
endmodule
module shift4bitright(c,a,b);
output [3:0]c;
input [3:0]a;
input [1:0]b;
wire [3:0]d=4'h0,d1=4'h0,d2=4'h0,d3=4'h0;
assign d[0]=a[3];
assign d1[0]=a[2]; assign d1[1]=a[3];
assign d2[0]=a[1]; assign d2[1]=a[2]; assign d2[2]=a[3];
assign d3[0]=a[0]; assign d3[1]=a[1];assign d3[2]=a[2];assign d3[3]=a[3];
mux4 m1(d,b,c[3]);
mux4 m2(d1,b,c[2]);
mux4 m3(d2,b,c[1]);
mux4 m4(d3,b,c[0]);
endmodule
`timescale 10ns/1ns
module shift4bitright_tb;
wire [3:0]c;
reg [3:0]a;
reg [1:0]b;
shift4bitright s1(.c(c),.a(a),.b(b));
initial begin
$monitor("a=%b b=%b c=%b",a,b,c);
a=4'h2;
b=2'd1;
#50
a=4'hf;
b=2'd1;
end
endmodule
This statement declared a wire type signal d as well as its driver cone (NOT initial value), which is a constant 0 in this case:
wire [3:0]d=4'h0;
Just below it, there's another a[3] driving d[0]:
assign d[0]=a[3];
This creates a multi-driven logic, hence x occurs.
To solve it, change it similar to:
wire [3:0] d;
assign d = {3'h0, a[3]};
I have Verilog code: magnitude comparator 4-bit.
I don't know what is wrong.
I have output without (a great than b) and (a less than b).
Where is my mistake?
`timescale 1ns/1ns
module magnitudecomparator(agtb,altb,aeqb,a,b);
input [3:0]a,b;
output agtb,altb,aeqb;
wire [3:0]x;
assign x=!(a^b);
assign agtb=(a[3]&(!b[3]))|(x[3]&a[2]&(!b[2]))|(x[3]&x[2]&a[1]&(!b[1]))|(x[3]&x[2]&x[1]&a[0]&(!b[0]));
assign altb=((!a[3])&b[3])|(x[3]&(!a[2])&b[2])|(x[3]&x[2]&(!a[1])&b[1])|(x[3]&x[2]&x[1]&(!a[0])&b[0]);
assign aeqb=x[3]&x[2]&x[1]&x[0];
endmodule
`timescale 1ns/1ns
module testmagnitudecomparator;
reg a,b;
wire agtb,aeqb,altb;
magnitudecomparator m0(agtb,altb,aeqb,a,b);
initial
begin
#10 a=4'b0110;b=4'b1110;
#20 a=4'b1101;b=4'b0111;
#30 a=4'b1011;b=4'b1011;
end
initial
$monitor($time, "THE VALUE OF INPUT IS a=%b ,b=%b AND OUTPUT IS agtb=%b ,aeqb=%b ,altb=%b",a,b,agtb,aeqb,altb);
endmodule
In your testbench, you connected 1-bit signals to 4-bit ports.
In the testmagnitudecomparator module, change:
reg a,b;
to:
reg [3:0]a,b;
Also, you could simplify your code:
assign agtb = (a > b);
assign altb = (a < b);
assign aeqb = (a == b);
Or you can also use a behavioral code by using if else statements..
always#(*)
begin
if(a>b)
agtb=1'b1;
else if(a<b)
altb=1'b1;
else
aeqb=q'b1;
end
I am working on a ripple carry adder using structural verilog, which is supposed to take in two random inputs and calculate accordingly.
The general rca I created calculated correctly, but for some reason I get weird outputs when I add a for loop and use the $random to generate.
Could someone kindly explain where I'm going wrong? Below is my code:
module full_adder(x,y,z,v,cout);
parameter delay = 1;
input x,y,z; //input a, b and c
output v,cout; //sum and carry out
xor #delay x1(w1,x,y);
xor #delay x2(v,w1,z);
and #delay a1(w2,z,y);
and #delay a2(w3,z,x);
and #delay a3(w4,x,y);
or #delay o1(cout, w2,w3,w4);
endmodule
module four_bit_adder(a,b,s,cout,cin);//four_bit_adder
input [15:0] a,b; //input a, b
input cin; //carry in
output [15:0] s; //output s
output cout; //carry out
wire [15:0] c;
full_adder fa1(a[0],b[0],cin,s[0],c0);
full_adder fa2(a[1],b[1],c0,s[1],c1);
.
.
.
full_adder fa16(a[15],b[15],c14,s[15],cout);
endmodule
module testAdder(a,b,s,cout,cin);
input [15:0] s;
input cout;
output [15:0] a,b;
output cin;
reg [15:0] a,b;
reg cin;
integer i;
integer seed1=4;
integer seed2=5;
initial begin
for(i=0; i<5000; i=i+1) begin
a = $random(seed1);
b = $random(seed2);
$monitor("a=%d, b=%d, cin=%d, s=%d, cout=%d",a,b,cin,s,cout);
$display("a=%d, b=%d, cin=%d, s=%d, cout=%d",a,b,cin,s,cout);
end
end
endmodule
Here are two lines from the output that I get:
a=38893, b=58591, cin=x, s= z, cout=z
a=55136, b=58098, cin=x, s= z, cout=z
This is a combinational circuit, so the output changes instantaneously as the input changes. But, here you are apply all the inputs at same timestamp which should not be done since the full_adder module provides 1-timestamp delay. This may not cause problems in this module, but may cause issues while modelling sequential logic. Add a minimum of #10 delay between inputs.
Also, $monitor executes on each change in the signal list, so no need to use it in for loop. Just initialize $monitor in initial condition.
cin is also not driven from the testbench. Default value of reg is 'x and that of wire is 'z. Here, cin is reg, so the default value is displayed, that is 'x
One more thing, you must instantiate the design in your testbench. And connect respective ports. The outputs from testbench act as inputs to your design and vice-versa. This is just like you instantiate full_adder module in four_bit_adder module in design.
Consider testadder as top level module and instantiate design in it. No need of declaring ports as input and output in this module. Declare the design input ports as reg or wire(example: reg [15:0] a when a is design input port) and output ports as wire (example: wire [15:0] sum when sum is design input port).
Referring to your question:
The general rca I created calculated correctly, but for some reason I get weird outputs when I add a for loop and use the $random to generate.
Instead of using $random, use $urandom_range() to generate random numbers in some range. Using SystemVerilog constraints constructs can also help. Refer this link.
Using $urandom_range shall eliminate use of seed1 and seed2, it shall generate random values with some random machine seed.
Following is the module testadder with some of the changes required:
module testAdder();
wire [15:0] s;
wire cout;
// output [15:0] a,b;
// output cin;
reg [15:0] a,b;
reg cin;
integer i;
integer seed1=4;
integer seed2=5;
// Instantiate design here
four_bit_adder fa(a,b,s,cout,cin);
initial begin
// Monitor here, only single time
$monitor("a=%d, b=%d, cin=%d, s=%d, cout=%d",a,b,cin,s,cout);
for(i=0; i<5000; i=i+1) begin
// Drive inputs with some delays.
#10;
// URANDOM_RANGE for input generation in a range
a = $urandom_range(0,15);
b = $urandom_range(0,15);
// a = $random(seed1);
// b = $random(seed2);
// Drive cin randomly.
cin = $random;
$display("a=%d, b=%d, cin=%d, s=%d, cout=%d",a,b,cin,s,cout);
end
end
endmodule
For more information, have a look at sample testbench at this link.
My design needs multiple multiplexers, all of them have two inputs and most are 32 bits wide. I started with designing the 32 bit, 2:1 multiplexer.
Now I need a 5 bit, 2:1 multiplexer and I want to reuse my 32 bit design. Connecting the inputs is easy (see code below), but I struggle to connect the output.
This is my code:
reg [4:0] a, b; // Inputs to the multiplexer.
reg select; // Select multiplexer output.
wire [4:0] result; // Output of the multiplexer.
multiplex32_2 mul({27'h0, a}, {27'h0, b}, select, result);
When I run the code through iverilog, I get a warning that says that the multiplexer expects a 32 bit output, but the connected bus is only 5 bit wide. The simulation shows the expected results, but I want to get rid of the warning.
Is there a way to tell iverilog to ignore the 27 unused bits of the multiplexer output or do I have to connect a 32 bit wide bus to the output of the multiplexer?
I don't know of a #pragma or something like that (similar to #pragma argsused from C) that can be used in Verilog.
Xilinx ISE, for example, has a feature called "message filtering", which allows the designer to silence specific warning messages. You find them once, select them, choose to ignore, and subsequent synthesis won't trigger those warnings.
Maybe you can design your multiplexer in a way you don't need to "waste" connections (not actually wasted though, as the synthesizer will prune unused connections from the netlist). A more elegant solution would be to use a parametrized module, and instantiate it with the required width. Something like this:
module mux #(parameter WIDTH=32) (
input wire [WIDTH-1:0] a,
input wire [WIDTH-1:0] b,
input wire sel,
output wire [WIDTH-1:0] o
);
assign o = (sel==1'b0)? a : b;
endmodule
This module has been tested with this simple test bench, which shows you how to instantiate a module with params:
module tb;
reg [31:0] a1,b1;
reg sel;
wire [31:0] o1;
reg [4:0] a2,b2;
wire [4:0] o2;
mux #(32) mux32 (a1,b1,sel,o1);
mux #(5) mux5 (a2,b2,sel,o2);
// Best way to instantiate them:
// mux #(.WIDTH(32)) mux32 (.a(a1),.b(b1),.sel(sel),o(o1));
// mux #(.WIDTH(5)) mux5 (.a(a2),.b(b2),.sel(sel),.o(o2));
initial begin
$dumpfile ("dump.vcd");
$dumpvars (1, tb);
a1 = 32'h01234567;
b1 = 32'h89ABCDEF;
a2 = 5'b11111;
b2 = 5'b00000;
repeat (4) begin
sel = 1'b0;
#10;
sel = 1'b1;
#10;
end
end
endmodule
You can test it yourself using this Eda Playground link:
http://www.edaplayground.com/x/Pkz
I think the problem relates to the output of the multiplexer which is still 5 bits wide. You can solve it by doing something like this:
reg [4:0] a, b; // Inputs to the multiplexer.
reg select; // Select multiplexer output.
wire [31:0] temp;
wire [4:0] result; // Output of the multiplexer.
multiplex32_2 mul({27'h0, a}, {27'h0, b}, select, temp);
assign result = temp[4:0];
This can be easily tested in http://www.edaplayground.com/ using the code below:
( I have re-used #mcleod_ideafix's code)
// Code your testbench here
// or browse Examples
module mux #(parameter WIDTH=32) (
input wire [WIDTH-1:0] a,
input wire [WIDTH-1:0] b,
input wire sel,
output wire [WIDTH-1:0] o
);
assign o = (sel==1'b0)? a : b;
endmodule
module tb;
reg [31:0] a,b;
wire [31:0] o;
wire [4:0] r;
reg sel;
initial begin
$dumpfile("dump.vcd"); $dumpvars;
a = 10; b = 20; sel = 1;
end
mux MM(a,b,sel,o);
assign r = o[4:0];
endmodule
Let me know if you are still getting a warning.