libfreenect2 example Protonect only showing raw feed? - linux

I figure the Protonect example in libfreenect2 is supposed to show more than just this raw feed?
I am running Linux Mint 17.2 and pocl 0.11 for OpenCL on an i7 4790.
The system has llvm-3.6 installed.
This is the output of clinfo.
Number of platforms 1
Platform Name Portable Computing Language
Platform Vendor The pocl project
Platform Version OpenCL 1.2 pocl 0.11
Platform Profile FULL_PROFILE
Platform Extensions cl_khr_icd
Platform Extensions function suffix POCL
Platform Name Portable Computing Language
Number of devices 1
Device Name pthread-Intel(R) Core(TM) i7-4790 CPU # 3.60GHz
Device Vendor pocl
Device Vendor ID 0x0
Device Version OpenCL 1.2 pocl
Driver Version 0.11
Device OpenCL C Version OpenCL C 1.2
Device Type CPU, Default
Device Profile FULL_PROFILE
Max compute units 8
Max clock frequency 4000MHz
Device Partition (core)
Max number of sub-devices 2
Supported partition types None
Max work item dimensions 3
Max work item sizes 18446744073709551615x18446744073709551615x18446744073709551615
Max work group size 4096
Preferred work group size multiple 8
Preferred / native vector sizes
char 16 / 16
short 8 / 8
int 4 / 4
long 2 / 2
half 8 / 8 (n/a)
float 4 / 4
double 2 / 2 (cl_khr_fp64)
Half-precision Floating-point support (n/a)
Single-precision Floating-point support (core)
Denormals No
Infinity and NANs Yes
Round to nearest Yes
Round to zero No
Round to infinity No
IEEE754-2008 fused multiply-add No
Support is emulated in software No
Correctly-rounded divide and sqrt operations No
Double-precision Floating-point support (cl_khr_fp64)
Denormals No
Infinity and NANs Yes
Round to nearest Yes
Round to zero No
Round to infinity No
IEEE754-2008 fused multiply-add No
Support is emulated in software No
Correctly-rounded divide and sqrt operations No
Address bits 64, Little-Endian
Global memory size 33643532288 (31.33GiB)
Error Correction support No
Max memory allocation 8410883072 (7.833GiB)
Unified memory for Host and Device Yes
Minimum alignment for any data type 128 bytes
Alignment of base address 128 bits (16 bytes)
Global Memory cache type None
Image support Yes
Max number of samplers per kernel 16
pocl warning: encountered incomplete implementation in clGetDeviceInfo.c:135
Max size for 1D images from buffer 0 pixels
pocl warning: encountered incomplete implementation in clGetDeviceInfo.c:137
Max 1D or 2D image array size 0 images
Max 2D image size 8192x8192 pixels
Max 3D image size 2048x2048x2048 pixels
Max number of read image args 128
Max number of write image args 128
Local memory type Global
Local memory size 8410883072 (7.833GiB)
Max constant buffer size 8410883072 (7.833GiB)
Max number of constant args 8
Max size of kernel argument 1024
Queue properties
Out-of-order execution No
Profiling Yes
Prefer user sync for interop Yes
Profiling timer resolution 0ns
Execution capabilities
Run OpenCL kernels Yes
Run native kernels Yes
pocl warning: encountered incomplete implementation in clGetDeviceInfo.c:257
printf() buffer size 0
Built-in kernels
Device Available Yes
Compiler Available Yes
Linker Available Yes
Device Extensions cl_khr_fp64 cl_khr_byte_addressable_store
NULL platform behavior
clGetPlatformInfo(NULL, CL_PLATFORM_NAME, ...) Portable Computing Language
clGetDeviceIDs(NULL, CL_DEVICE_TYPE_ALL, ...) Success [POCL]
clCreateContext(NULL, ...) [default] Success [POCL]
clCreateContextFromType(NULL, CL_DEVICE_TYPE_CPU) Success (1)
Platform Name Portable Computing Language
Device Name pthread-Intel(R) Core(TM) i7-4790 CPU # 3.60GHz
clCreateContextFromType(NULL, CL_DEVICE_TYPE_GPU) No devices found in platform
clCreateContextFromType(NULL, CL_DEVICE_TYPE_ACCELERATOR) No devices found in platform
clCreateContextFromType(NULL, CL_DEVICE_TYPE_CUSTOM) No devices found in platform
clCreateContextFromType(NULL, CL_DEVICE_TYPE_ALL) Success (1)
Platform Name Portable Computing Language
Device Name pthread-Intel(R) Core(TM) i7-4790 CPU # 3.60GHz
ICD loader properties
ICD loader Name OpenCL ICD Loader
ICD loader Vendor OCL Icd free software
ICD loader Version 2.1.3
ICD loader Profile OpenCL 1.2
Any thoughts as to what could be wrong? This is my first time using OpenCL on a CPU instead of a GPU and also my first time trying anything with a Kinect so I am not very familiar. Thanks for the help!

Your OpenCL doesn't matter, because you're not using OpenCL. In the output you can see OpenGLDepthPacketProcessor, which is the default in protonect. I think there has been some trouble with that on Linux recently. Try starting protonect with the cl command line parameter:
./protonect cl
That should make sure the OpenCL implementation is used.
You can also try the cpu parameter instead, using neither OpenGL nor OpenCL. That will be way slower, but should at least work without worrying about the correct OpenGL/OpenCL drivers.

Related

I am using BIOS J51 v01.35 on which version is on intel TM i5

My system is Intel(R) Core(TM) i5-2500 CPU # 3.30GHz
and bios is version J51 v01.35
release data of bios 01/10/2012
So Should I believe I am using SMBIOS 2 or SMBios 3
On wiki.Osdev there are no docs for version 3 but there are for version 2 for SMBIOS
You can find this information using dmidecode:
# dmidecode
...
Getting SMBIOS data from sysfs.
SMBIOS 2.7 present.
285 structures occupying 19154 bytes.
Table at 0x0EFC201F.
...

Papi_avail no events available - Unknown libpfm4 related error

I just made a fresh install of Ubuntu 20 on an AMD Ryzen 5000 series. I installed papi tools 6 by following the install instructions. The installation was succsessful and I verified the installed version:
$ sudo papi_version
PAPI Version: 6.0.0.0
Then, when I verified the available events, I got none:
$ sudo papi_avail
Available PAPI preset and user defined events plus hardware information.
--------------------------------------------------------------------------------
PAPI version : 6.0.0.0
Operating system : Linux 5.8.0-55-generic
Vendor string and code : AuthenticAMD (2, 0x2)
Model string and code : AMD Ryzen 9 5900 12-Core Processor (33, 0x21)
CPU revision : 0.000000
CPUID : Family/Model/Stepping 25/33/0, 0x19/0x21/0x00
CPU Max MHz : 6084
CPU Min MHz : 2200
Total cores : 24
SMT threads per core : 2
Cores per socket : 12
Sockets : 1
Cores per NUMA region : 24
NUMA regions : 1
Running in a VM : no
Number Hardware Counters : 0
Max Multiplex Counters : 384
Fast counter read (rdpmc): yes
--------------------------------------------------------------------------------
================================================================================
PAPI Preset Events
================================================================================
Name Code Avail Deriv Description (Note)
PAPI_L1_DCM 0x80000000 No No Level 1 data cache misses
PAPI_L1_ICM 0x80000001 No No Level 1 instruction cache misses
PAPI_L2_DCM 0x80000002 No No Level 2 data cache misses
PAPI_L2_ICM 0x80000003 No No Level 2 instruction cache misses
PAPI_L3_DCM 0x80000004 No No Level 3 data cache misses
PAPI_L3_ICM 0x80000005 No No Level 3 instruction cache misses
PAPI_L1_TCM 0x80000006 No No Level 1 cache misses
PAPI_L2_TCM 0x80000007 No No Level 2 cache misses
PAPI_L3_TCM 0x80000008 No No Level 3 cache misses
PAPI_CA_SNP 0x80000009 No No Requests for a snoop
PAPI_CA_SHR 0x8000000a No No Requests for exclusive access to shared cache line
PAPI_CA_CLN 0x8000000b No No Requests for exclusive access to clean cache line
PAPI_CA_INV 0x8000000c No No Requests for cache line invalidation
PAPI_CA_ITV 0x8000000d No No Requests for cache line intervention
PAPI_L3_LDM 0x8000000e No No Level 3 load misses
PAPI_L3_STM 0x8000000f No No Level 3 store misses
PAPI_BRU_IDL 0x80000010 No No Cycles branch units are idle
PAPI_FXU_IDL 0x80000011 No No Cycles integer units are idle
PAPI_FPU_IDL 0x80000012 No No Cycles floating point units are idle
PAPI_LSU_IDL 0x80000013 No No Cycles load/store units are idle
PAPI_TLB_DM 0x80000014 No No Data translation lookaside buffer misses
PAPI_TLB_IM 0x80000015 No No Instruction translation lookaside buffer misses
PAPI_TLB_TL 0x80000016 No No Total translation lookaside buffer misses
PAPI_L1_LDM 0x80000017 No No Level 1 load misses
PAPI_L1_STM 0x80000018 No No Level 1 store misses
PAPI_L2_LDM 0x80000019 No No Level 2 load misses
PAPI_L2_STM 0x8000001a No No Level 2 store misses
PAPI_BTAC_M 0x8000001b No No Branch target address cache misses
PAPI_PRF_DM 0x8000001c No No Data prefetch cache misses
PAPI_L3_DCH 0x8000001d No No Level 3 data cache hits
PAPI_TLB_SD 0x8000001e No No Translation lookaside buffer shootdowns
PAPI_CSR_FAL 0x8000001f No No Failed store conditional instructions
PAPI_CSR_SUC 0x80000020 No No Successful store conditional instructions
PAPI_CSR_TOT 0x80000021 No No Total store conditional instructions
PAPI_MEM_SCY 0x80000022 No No Cycles Stalled Waiting for memory accesses
PAPI_MEM_RCY 0x80000023 No No Cycles Stalled Waiting for memory Reads
PAPI_MEM_WCY 0x80000024 No No Cycles Stalled Waiting for memory writes
PAPI_STL_ICY 0x80000025 No No Cycles with no instruction issue
PAPI_FUL_ICY 0x80000026 No No Cycles with maximum instruction issue
PAPI_STL_CCY 0x80000027 No No Cycles with no instructions completed
PAPI_FUL_CCY 0x80000028 No No Cycles with maximum instructions completed
PAPI_HW_INT 0x80000029 No No Hardware interrupts
PAPI_BR_UCN 0x8000002a No No Unconditional branch instructions
PAPI_BR_CN 0x8000002b No No Conditional branch instructions
PAPI_BR_TKN 0x8000002c No No Conditional branch instructions taken
PAPI_BR_NTK 0x8000002d No No Conditional branch instructions not taken
PAPI_BR_MSP 0x8000002e No No Conditional branch instructions mispredicted
PAPI_BR_PRC 0x8000002f No No Conditional branch instructions correctly predicted
PAPI_FMA_INS 0x80000030 No No FMA instructions completed
PAPI_TOT_IIS 0x80000031 No No Instructions issued
PAPI_TOT_INS 0x80000032 No No Instructions completed
PAPI_INT_INS 0x80000033 No No Integer instructions
PAPI_FP_INS 0x80000034 No No Floating point instructions
PAPI_LD_INS 0x80000035 No No Load instructions
PAPI_SR_INS 0x80000036 No No Store instructions
PAPI_BR_INS 0x80000037 No No Branch instructions
PAPI_VEC_INS 0x80000038 No No Vector/SIMD instructions (could include integer)
PAPI_RES_STL 0x80000039 No No Cycles stalled on any resource
PAPI_FP_STAL 0x8000003a No No Cycles the FP unit(s) are stalled
PAPI_TOT_CYC 0x8000003b No No Total cycles
PAPI_LST_INS 0x8000003c No No Load/store instructions completed
PAPI_SYC_INS 0x8000003d No No Synchronization instructions completed
PAPI_L1_DCH 0x8000003e No No Level 1 data cache hits
PAPI_L2_DCH 0x8000003f No No Level 2 data cache hits
PAPI_L1_DCA 0x80000040 No No Level 1 data cache accesses
PAPI_L2_DCA 0x80000041 No No Level 2 data cache accesses
PAPI_L3_DCA 0x80000042 No No Level 3 data cache accesses
PAPI_L1_DCR 0x80000043 No No Level 1 data cache reads
PAPI_L2_DCR 0x80000044 No No Level 2 data cache reads
PAPI_L3_DCR 0x80000045 No No Level 3 data cache reads
PAPI_L1_DCW 0x80000046 No No Level 1 data cache writes
PAPI_L2_DCW 0x80000047 No No Level 2 data cache writes
PAPI_L3_DCW 0x80000048 No No Level 3 data cache writes
PAPI_L1_ICH 0x80000049 No No Level 1 instruction cache hits
PAPI_L2_ICH 0x8000004a No No Level 2 instruction cache hits
PAPI_L3_ICH 0x8000004b No No Level 3 instruction cache hits
PAPI_L1_ICA 0x8000004c No No Level 1 instruction cache accesses
PAPI_L2_ICA 0x8000004d No No Level 2 instruction cache accesses
PAPI_L3_ICA 0x8000004e No No Level 3 instruction cache accesses
PAPI_L1_ICR 0x8000004f No No Level 1 instruction cache reads
PAPI_L2_ICR 0x80000050 No No Level 2 instruction cache reads
PAPI_L3_ICR 0x80000051 No No Level 3 instruction cache reads
PAPI_L1_ICW 0x80000052 No No Level 1 instruction cache writes
PAPI_L2_ICW 0x80000053 No No Level 2 instruction cache writes
PAPI_L3_ICW 0x80000054 No No Level 3 instruction cache writes
PAPI_L1_TCH 0x80000055 No No Level 1 total cache hits
PAPI_L2_TCH 0x80000056 No No Level 2 total cache hits
PAPI_L3_TCH 0x80000057 No No Level 3 total cache hits
PAPI_L1_TCA 0x80000058 No No Level 1 total cache accesses
PAPI_L2_TCA 0x80000059 No No Level 2 total cache accesses
PAPI_L3_TCA 0x8000005a No No Level 3 total cache accesses
PAPI_L1_TCR 0x8000005b No No Level 1 total cache reads
PAPI_L2_TCR 0x8000005c No No Level 2 total cache reads
PAPI_L3_TCR 0x8000005d No No Level 3 total cache reads
PAPI_L1_TCW 0x8000005e No No Level 1 total cache writes
PAPI_L2_TCW 0x8000005f No No Level 2 total cache writes
PAPI_L3_TCW 0x80000060 No No Level 3 total cache writes
PAPI_FML_INS 0x80000061 No No Floating point multiply instructions
PAPI_FAD_INS 0x80000062 No No Floating point add instructions
PAPI_FDV_INS 0x80000063 No No Floating point divide instructions
PAPI_FSQ_INS 0x80000064 No No Floating point square root instructions
PAPI_FNV_INS 0x80000065 No No Floating point inverse instructions
PAPI_FP_OPS 0x80000066 No No Floating point operations
PAPI_SP_OPS 0x80000067 No No Floating point operations; optimized to count scaled single precision vector operations
PAPI_DP_OPS 0x80000068 No No Floating point operations; optimized to count scaled double precision vector operations
PAPI_VEC_SP 0x80000069 No No Single precision vector/SIMD instructions
PAPI_VEC_DP 0x8000006a No No Double precision vector/SIMD instructions
PAPI_REF_CYC 0x8000006b No No Reference clock cycles
--------------------------------------------------------------------------------
Of 108 possible events, 0 are available, of which 0 are derived.
No events detected! Check papi_component_avail to find out why.
So I followed the instructions and I ran the papi_component_avail:
papi_component_avail
Available components and hardware information.
--------------------------------------------------------------------------------
PAPI version : 6.0.0.0
Operating system : Linux 5.8.0-55-generic
Vendor string and code : AuthenticAMD (2, 0x2)
Model string and code : AMD Ryzen 9 5900 12-Core Processor (33, 0x21)
CPU revision : 0.000000
CPUID : Family/Model/Stepping 25/33/0, 0x19/0x21/0x00
CPU Max MHz : 6084
CPU Min MHz : 2200
Total cores : 24
SMT threads per core : 2
Cores per socket : 12
Sockets : 1
Cores per NUMA region : 24
NUMA regions : 1
Running in a VM : no
Number Hardware Counters : 0
Max Multiplex Counters : 384
Fast counter read (rdpmc): yes
--------------------------------------------------------------------------------
Compiled-in components:
Name: perf_event Linux perf_event CPU counters
\-> Disabled: Unknown libpfm4 related error
Name: perf_event_uncore Linux perf_event CPU uncore and northbridge
\-> Disabled: No uncore PMUs or events found
Active components:
--------------------------------------------------------------------------------
I tried applying the fix explained in the stack overflow question papi_avail: No events available - 32308175 which in the past has worked on my Ubuntu 18 running an Intel 6700HQ, but with no avail here. Of course, the problem descriptions were different.I am uncertain on how to resolve the "Unknown libpfm4 related error" error.
I also tried installing the current availabe version of Papi using the "apt get install papi tools"
sudo apt-get update
sudo apt-get install papi-tools
The installation went fine but I keep getting the same errore messages. What have I missed?
Your CPU is part of the AMD ZEN3 family. libpfm4 seems to support this CPU architecture family from v4.12.0. If you have papi version 6.0.0.1 or less, it comes with a built-in version of libpfm4 that is older than v4.12.0 so I suppose papi is expected not to work in that case?
Nevertheless, we are still experiencing the same issue when installing the master branch of papi (that comes with a libpfm4 version that should support AMD ZEN3 according to documentation).

Unable to Write in MSR_EBC_FREQUENCY_ID (0x2C) on Pentium 4 Processor

I want to modify "Core Clock Frequency to System Bus Frequency Ratio BITS[31:24]" in register MSR_EBC_FREQUENCY_ID (0x2C) on Pentium 4 desktop processor by developing a Linux Kernel Module (LKM/Driver). Below the processor details.
Name: Intel(R) Pentium(R) 4,
Type: 0,
Family: 15 (0xF),
Model: 2,
Stepping: 7
Ref: https://software.intel.com/sites/default/files/managed/22/0d/335592-sdm-vol-4.pdf (Page-316, Table 2-44).
But the write call (wrmsr) unable to write the desired value in the register!!!
Please let me know how can I write on this MSR? Do I need to do other things to write on this register?
Thanks in advance.
These bits are read-only according to Intel SDM:
31:24 Core Clock Frequency to System Bus Frequency Ratio (R)

32 bit Datapath RISCV core

I'm trying to parametrize the rocket core by changing the configuration in PublicConfig.scala.
However, when I change XprLen and L1D_SETS to 32, I have a compilation problem.
What is the proper way to genarate a 32 bit data path with the Rocket Chip Generator, if possible?
The Rocket-chip does not currently support generating a 32b processor.
While the required changes to the datapath would be minimal, the host-target interface for communicating to the front-end server (as Rocket currently only runs in a tethered mode) has only been spec'ed out for 64b cores.
ALso, L1D_SETS is the number of "sets" in the L1 data-cache (such that L1D_WAYS * L1D_SETS * 64 bytes per line is the total cache capacity in bytes).

Where to start learning about linux DMA / device drivers / memory allocation

I'm porting / debugging a device driver (that is used by another kernel module) and facing a dead end because dma_sync_single_for_device() fails with an kernel oops.
I have no clue what that function is supposed to do and googling does not really help, so I probably need to learn more about this stuff in total.
The question is, where to start?
Oh yeah, in case it is relevant, the code is supposed to run on a PowerPC (and the linux is OpenWRT)
EDIT:
On-line resources preferrable (books take a few days to be delivered :)
On-line:
Anatomy of the Linux slab allocator
Understanding the Linux Virtual Memory Manager
Linux Device Drivers, Third Edition
The Linux Kernel Module Programming Guide
Writing device drivers in Linux: A brief tutorial
Books:
Linux Kernel Development (2nd Edition)
Essential Linux Device Drivers ( Only the first 4 - 5 chapters )
Useful Resources:
the Linux Cross Reference ( Searchable Kernel Source for all Kernels )
API changes in the 2.6 kernel series
dma_sync_single_for_device calls dma_sync_single_range_for_cpu a little further up in the file and this is the source documentation ( I assume that even though this is for arm the interface and behavior are the same ):
/**
380 * dma_sync_single_range_for_cpu
381 * #dev: valid struct device pointer, or NULL for ISA and EISA-like devices
382 * #handle: DMA address of buffer
383 * #offset: offset of region to start sync
384 * #size: size of region to sync
385 * #dir: DMA transfer direction (same as passed to dma_map_single)
386 *
387 * Make physical memory consistent for a single streaming mode DMA
388 * translation after a transfer.
389 *
390 * If you perform a dma_map_single() but wish to interrogate the
391 * buffer using the cpu, yet do not wish to teardown the PCI dma
392 * mapping, you must call this function before doing so. At the
393 * next point you give the PCI dma address back to the card, you
394 * must first the perform a dma_sync_for_device, and then the
395 * device again owns the buffer.
396 */
Understanding The Linux Kernel?
The chapters of the Linux Device Drivers book (in the same series as Understanding the Linux Kernel, recommended by #Matthew Flaschen) might be useful.
You can download the indiivudal chapters from the LWN Website. Chapter 16 deals with DMA.

Resources