How do you use commands like #define and !include in linux makefile for the g++ compiler?
My understanding is that # creates a comment line so wont #define just be a comment?
Thanks for the help
I typically define a variable at the top of the file, and set it equal to the #define values I want like this:
DEFINES=-DSOMETHING -DSOMETHING_ELSE
For includes, g++ accepts search paths from the command line with -I.
For the makefile you can do the same thing, just make a variable and add the paths:
INCLUDES=-I/path -I/path2
The makefile then just calls the compiler as
g++ $(DEFINES) $(INCLUDES) file.cpp
Check out this example
# I am a comment, and I want to say that the variable CC will be
# the compiler to use.
CC=g++
# Hey!, I am comment number 2. I want to say that CFLAGS will be the
# options I'll pass to the compiler.
CFLAGS=-c -Wall
all: hello
hello: main.o factorial.o hello.o
$(CC) main.o factorial.o hello.o -o hello
main.o: main.cpp
$(CC) $(CFLAGS) main.cpp
factorial.o: factorial.cpp
$(CC) $(CFLAGS) factorial.cpp
hello.o: hello.cpp
$(CC) $(CFLAGS) hello.cpp
clean:
rm *o hello
for more information check these:
http://mrbook.org/blog/tutorials/make/
http://www.cs.umd.edu/class/fall2002/cmsc214/Tutorial/makefile.html
Related
I have a problem trying to create a Makefile that compile multiple sorces, generate only a shared library and make an exe with another file wiht the main function.
The sorces also have dependencies.
My Makefile is
CC=gcc
CFLAGS=-Wall -g
BINS=libsensorMotor.so maintarget
all: $(BINS)
libsensorMotor.o: libsensorMotor.cpp sensorMotor.h Adafruit_ADS1015.cpp Adafruit_ADS1015.h wiringPiI2C.c wiringPiI2C.h enumADCGain.h
$(CC) $(CFLAGS) -c libsensorMotor.cpp Adafruit_ADS1015.cpp wiringPiI2C.c
libsensorMotor.so: libsensorMotor.cpp sensorMotor.h
$(CC) $(CFLAGS) -fPIC -shared -o $# libsensorMotor.cpp -lc
maintarget: maintarget.c
$(CC) $(CFLAGS) -o $# $^ -L. -lsensorMotor -pthread
clean:
rm *.o $(BINS)
The script show the errors:
libsensorMotor.so Undefined reference to 'functionXXXX'
maintarget contains the main and use libsensorMotor as a shared library. libsensorMotor depends and include all the rest of the files
The error mention all the functions that libsensorMotor uses from the include sources.
I only need to generate a correct libsensorMotor.so that can use as shared library from any other main file. Internet has many tutorials but are unclear, weird and complicated, and not show how do this simple.
Is not Makefile problem, simply the line
gcc -pthread -lm -o maintarget maintarget.c libsensorMotor.cpp Adafruit_ADS1015.cpp wiringPiI2C.c
sends same error, the compiler not recongnice the function inside the pthread_create while compile C and C++ with gcc
Here is a tutorial for make file in Linux: http://mrbook.org/tutorials/make/
Here is a make file example:
all: hello
hello: main.o factorial.o hello.o
g++ main.o factorial.o hello.o -o hello
main.o: main.cpp
g++ -c main.cpp
factorial.o: factorial.cpp
g++ -c factorial.cpp
hello.o: hello.cpp
g++ -c hello.cpp
clean:
rm -rf *o hello
For me this line is confusing main.o: main.cpp
What does it mean? As I understand, it means target main.o has a main.cpp dependency. But there is no target with main.cpp
It means a target (main.o) has a dependency (main.cpp) which that dependency (main.cpp) itself is not a target. So what is it (main.cpp)?
main.cpp is a file.
From the extension we expect it to be a c++ source file, and the associated rule suggest that this is the case.
The rule will be exectuted any time that main.cpp is newer than main.o (which is also a file).
main.cpp is your source code. The fact that there is no target for main.cpp just means that Make has no way to generate that file. You are expected to create it yourself.
I got an assignment to improve running time of some code. The only problem is, I can't even compile it to run it on my machine in the first place. Every time I try, it stops somewhere in the midst of compiling saying this:
"undefined reference to `boost::re_detail::put_mem_block(void*)'
collect2: ld returned 1 exit status make: * [cpu] Error 1"
This is how makefile looks:
SHELL = /bin/bash
OBJECTS = main.o atom.o molecule.o charges.o pdb.o asa.o amino.o chain.o addition.o string_operation.o pdb_peptide.o protein_chain.o residue_atom.o chain_residue.o residue_contact.o atom_grid.o circles.o atom_space_calculations.o
OBJDIR = obj
VPATH = src:src/ext:$(OBJDIR)
CFLAGS = -O3 -Wall -lm -lboost_regex -L/usr/local/boost/lib
HDIRS = src,src/ext,src/qt_redistributable, usr/lib, usr/local/lib, usr/local/lib/include/boost, /usr/local/lib/lib/
IOPTS = $(addprefix -I, $(HDIRS))
cpu : $(addprefix $(OBJDIR)/, $(OBJECTS) $(CPUOBJS))
g++ $(CFLAGS) -o mcpu $^
$(OBJDIR)/%.o : %.cpp
g++ $(CFLAGS) $(IOPTS) -c $< -o $#
clean :
rm obj/*.o $(PROG)
I'm using Linux Mint x64 and I have tried everything I googled out. Installed the whole boost library in usr/local/lib (for no obvious reason because it didn't help), tried to edit LD PATH (I'm very new to Linux and I have no idea if that went right) and lots of stuff, but this thing doesn't seem to go through. Any help appreciated.
One problem with your makefile happens when you link your program. As you can see in these questions with g++ the order of your arguments at link time is really important. You need to put your libraries after your object files. One easy way to solve would be separating your linker flags (LDFLAGS) from the compiler flags (CFLAGS), and then putting LDFLAGS after $^ (your object files) in the link command.
CFLAGS = -O3 -Wall
LDFLAGS = -L/usr/local/boost/lib -lm -lboost_regex
cpu : $(addprefix $(OBJDIR)/, $(OBJECTS) $(CPUOBJS))
g++ $(CFLAGS) -o mcpu $^ $(LDFLAGS)
$(OBJDIR)/%.o : %.cpp
g++ $(CFLAGS) $(IOPTS) -c $< -o $#
As can be seen in the Catalogue of Built-In Rules:
Linking a single object file
n is made automatically from n.o by running the linker (usually called
ld) via the C compiler. The precise recipe used is:
$(CC) $(LDFLAGS) n.o $(LOADLIBES) $(LDLIBS)
and Variables Used by Implicit Rules:
LDFLAGS
Extra flags to give to compilers when they are supposed to invoke the linker,
ld, such as -L. Libraries (-lfoo) should be added to the LDLIBS variable
instead.
So in this case -lboost_regex should be set or added to LDLIBS, not LDFLAGS.
I'm facing a silly problem with GNU makefile.
I want to define two targets to build a c program; one with debugging and the other without.
runNoDebug: setNoDeb objs runMe
runDebug: setDeb objs runMe
setNoDeb:
{EXPORT} MyDEBUG= -O3
setDeb:
{EXPORT} MyDEBUG="-DDEBUG=1 -g"
objs: cFiles
$(CC) -o $# $^ $(cFiles) $(CFLAGS) $(LIBS) $(MYDEBUG)
runme: objs
./oo
Errors arise on running this makefile, the command to set debugging executes on the subshell causing errors. If "Export" is added, the variable is defined in that subshell.
I want to define this variable in the makefile iteself to be used while building objects.
Is it possible? Or should I duplicate the "objs: cFiles" target?
You need target-specific variable values :
This feature allows you to define different values for the same variable, based on the target that make is currently building.
runNoDebug: setNoDeb runMe
runDebug: setDeb runMe
setNoDeb: CFLAGS += -O3
setNoDeb: objs
setDeb: CPPFLAGS += -DDEBUG=1
setDeb: CFLAGS += -g
setDeb: objs
objs: $(cFiles)
$(CC) $(CFLAGS) $^ $(LIBS) -o $#
I have the makefile below and a directory tree :
->project/src/main.c, func.c,
Makefile
->project/exe/
->project/inc/
->project/obj/
cc=gcc
cflags=-c
obj=../obj
exe=../exe
inc=../inc
prog.exe: main.o func.o
$(cc) main.o func.o -o $(exe)/prog.exe
main.o: main.c $(inc)/defs.h
$(cc) $(cflags) main.c
mv main.o $(obj)/
func.o: func.c $(inc)/defs.h
$(cc) $(cflags) func.c
mv func.o $(obj)/
The problem is, the second actions below main.o and func.o (those start with mv) doesn't work (i.e main.o isn't moved to the /obj directory). Is there a problem in the syntax of makefile or anything else?
One apparent problem is that the makefile doesn't build the targets it's supposed to build. I.e.:
prog.exe: main.o func.o
$(cc) main.o func.o -o $(exe)/prog.exe
Doesn't build prog.exe, rather it builds $(exe)/prog.exe, which is a different file. A fix would be:
$(exe)/prog.exe: $(obj)/main.o $(obj)/func.o
$(cc) $^ -o $#
Prefer using automatic variables for the names of input and output files to avoid duplication and silly typos.
You may take care of the indentation with make. It needs real tabs.
See https://superuser.com/questions/224434/what-is-the-character-used-to-indent-the-make-file-rule-recipe