Tick-including a header file inside package in systemverilog - verilog

Question

Hi I've following scenario and it's not working for me.
file: a.svh
a.svh defines some parameters and functions- let's say function xyz(b)
file b.sv
package b;
`include "a.svh"
typedef logic[(xyz(10)-1):0] h;
endpackage
Now the issue is, b.sv can't find xyz function in it's scope, even thought I'm tick-including a.svh in b.sv. Everything works fine if I don't use a package in b.sv file. (comment out package b and endpackage lines).
//package b;
`include "a.svh"
typedef logic[(xyz(10)-1):0] h;
//endpackage
Is it an illigal case in systemverilog?

Answer 1

I recreated your scenario on EDAplayground. I didn't get any errors.
A function is intended to be evaluated during simulation. Some simulators support evaluating function during compile/elaboration, but it doesn't appear to be a requirement.
SystemVerilog also has let, which is more appropriate for for compile time evaluation (it supports simulation time as well). Refer to IEEE Std 1800-2012 § 11.13 Let construct:
let declarations can be used for customization and can replace the text macros in many cases. The let construct is safer because it has a local scope, while the scope of compiler directives is global within the compilation unit. Including let declarations in packages (see Clause 26) is a natural way to implement a well-structured customization for the design code.
a.svh
function int xyz_func(int b);
return b;
endfunction
let xyz_let(b) = b;
design.sv (equivalent to your b.sv, EDAplayground requires design.sv to exist)
package b;
`include "a.svh"
typedef logic[(xyz_func(10)-1):0] hf;
typedef logic[xyz_let(10):1] hl;
endpackage
testbench.sv
module tb;
import b::*;
hf myhf;
hl myhl;
initial begin
myhf = -1;
myhl = -1;
$display("hf:%b left:%0d right:%0d", myhf, $left(myhf), $right(myhf));
$display("hl:%b left:%0d right:%0d", myhl, $left(myhl), $right(myhl));
end
endmodule
Output:
hf:1111111111 left:9 right:0
hl:1111111111 left:10 right:1