How to connect my clockDivider into this verilog program with Quartus II - verilog

Question

Code:
TestBench.v:
// ============================================================
//
// Traffic light tester module.
//
// We clock the device as usual, supply reset, and eventually "push
// the walk button" to activate the traffic light.
//
// ============================================================
// `timescale 1 ns / 1 ns
module TestBench;
reg clk; // Clock into the FPGA
reg walk; // A button that causes the walk light to go on
reg reset; // The reset line to your design
wire green; // The green light on Dodge Street
wire yellow; // The yellow light on ...
wire red; // The red light on ...
wire go; // The walk light for the pedestrian
wire stop; // The "don't walk" light
// Here is your FPGA chip
Traffic yourChip( reset, clk, walk, green, yellow, red, go, stop );
// Provide clocking to the FPGA
always
begin
#10 clk = ~clk;
end
// Start up code.
initial
begin
clk = 0;
walk = 0;
reset = 1;
#100 reset = 0;
end
// Eventually we want to "push the walk button" which causes the
// traffic lights to cycle yellow, red, then back to green.
// Also, we want to stop the sim at some point too.
initial
begin
#1000 walk = 1;
#100 walk = 0;
#100000 $stop;
end
endmodule // QuasiTestBench
clockDivder.v:
module clockDivider(
input wire clock,
input wire reset,
output wire dividedClk
);
reg [127:0] counter;
always #(posedge clock or posedge reset)
begin
if(reset == 1)
counter <=0;
else
counter <= counter + 1;
end
assign dividedClk = counter[127];
endmodule
Traffic.v:
module Traffic( reset, clock, walk, green, yellow, red, walkLight, handLight);
input wire reset;
input wire clock;
input wire walk;
output reg green, yellow, red, walkLight, handLight;
reg[2:0] state;
reg[3:0] count;
//we want some kind of state machine here.
//let's define some states
parameter s0 = 0 //green
, s1=1 //yellow
, s2=2; //red
reg[3:0] timeButtonPushed;
//clockDivider myClock(clock, reset);
always #(posedge clock or posedge reset)
begin
if (reset == 1)
begin
state <= s0; //default to green light on reset.
handLight = 1;
green = 1;
timeButtonPushed = 0;
count <= 0;
end
else
case(state)
s0:
begin
if(walk == 1)
begin
//compute 10s timeout before switch to yellow
//requires us to capture some info about time button pushed
timeButtonPushed = count; //record time button was pushed
end
else
if(timeButtonPushed == (count - 10))
begin
state = s1; //We've reached countdown state set light to yellow.
green = 0;
yellow = 1;
end
count = count + 1;
end
s1:
begin
if(timeButtonPushed == (count - 15)) //We've reached timeout for yellow light.
begin
state = s2; //move to red state
handLight = 0;
walkLight = 1;
red = 1;
end
count = count + 1;
end
s2:
begin
if(timeButtonPushed == count - 45)
begin
state = s0; //move back to green state
red = 0;
walkLight = 0;
handLight = 1;
green = 0;
timeButtonPushed = 0;
end
count = count + 1;
end
default: state <= s0;
endcase
end
endmodule
I've tried to instantiate the clockDivider in the TestBench, and I've also tried to instantiate it in Traffic.v attempting to insert it in between the clock and the input clk wire in Traffic.v
Ideally I'd like a solution that shows me the correct way to wire the clockDivider properly, however if there are other ways--even if hack-ish to get it done I'd appreciate it.
I've also tried forgetting clockDivider.v entirely and replaced the clock code with this:
reg [127:0] counter;
always
begin
if(reset == 1)
counter <=0;
else if(counter == 126)
assign clk = ~clk;
else
counter <= counter + 1;
end
But that too appears to fail.

Answer 1

Firstly, in your sample instantiation, you aren't connencting any signal to the dividedClk output. As such, it's hard to see what you're trying to use it for. You're allowed to omit connections, but you need the delimiting commas. Try: clockDivider myClock(clock, reset,);
Secondly, generating a clock with logic is poor design - you'll have major issues with timing. Logic signals can't be properly loaded onto the clock tree network, so you can get a large clock skew as a result. Instead, use your counter as an enable signal to any "slower" registers and use the global clock, or make use of a PLL/DLL to generate a new (slower) clock signal.
As an example of the first:
reg enable;
reg [127:0] counter;
parameter NUMBEROFCYCLES = 100;
always #(posedge clk)
begin
if (reset) enable <= 0;
else if (counter == NUMBEROFCYCLES) enable <= 1;
else enable <= 0;
end
always #(posedge clk)
begin
if (reset) counter <= 0;
else if (counter == NUMBEROFCYCLES) counter <= 0;
else counter <= counter + 1;
end
always #(posedge clk)
begin
if (reset) <<reset some signals>>
else if (enable) <<change some signals>>
else <<signals <= signals>>
end