I tried to use Digital Clock Manager (DCM) and double the input clock. iSim (Xilinx simulation tool) gives the correct result, but in Modelsim the output clock is always zero.
I always compile the unisims folder (that consist of IBUFG, DCM and BUFG modules in xilinx software) in the library of my project in modelsim.
According to the Russel Answer I used Xilinx Core Generator. I want the frequency of CLKFX to be double of CLKIN. As you see in the following pictures, the results of iSim (Xilinx simulator) is correct, but in Modelsim CLKFX is always zero :
iSim results (Xilinx Simulator) :
Modelsim results :
If you think you're not setting up the DCM correctly, you need to read the documentation about DCMs and how they work. If you search for Xilinx Library Guide (+FPGA Name) you'll find all of the Primitives that are available in your device. Or you can look at the full list here:
Xilinx Library Guides
If you're still having trouble after looking at all of your parameters, you can try using CoreGen to generate your DCM for you. CoreGen will ensure that you do not make any mistakes or instantiate something in an invalid configuration. The output of CoreGen is a .vhd file that you can drop into your modelsim project and simulate with that.
Related
I am curious to learn about the technology which is used in generating software clock in simulators. The frequency of my machine is only ~2.4GHz but I can generate up to 500THz clock using a simulator(Refer below system Verilog snippet ).
`timescale 1fs/1fs;//This is the minimum time-unit and precision that can be used to generate 500THz clock
module temp();
bit clk_b;
always #1 clk_b =~ clk_b ;
endmodule
Is this higher frequency just a software illusion or does it have any link with CPU crystal oscillator?
The simulation does not "run" in realtime. So it will compute the result for the steps and if it is done it is done. Which means that the ratio between number of required steps (as well as problem complexity) and your computer performance will define how much time the simulation will need to finish. The timescale setting of the simulation is just what it says: a way to relate the simulation steps into a time(scale).
So it is really an "illusion" if you want to call it so.
SystemVerilog is a HVL i.e. a Hardware Verification Language. It is (mostly) used to verify hardware designs.
The main purpose of the language is to provide a platform where one can create logic to verify the DUT by running simulations i.e. generating different operating conditions for the DUT and checking how it behaves under each condition. But this does not necessarily mean that DUT is supposed to operate in such extreme conditions generated by the SystemVerilog testbench.
When you are generating 500THz clock from your testbench and checking the behaviour of your DUT, you are making sure that the DUT is not (virtually) going to break down even in such extreme conditions. But please note that this is just a virtual environment you have created and not the actual environment under which the DUT once synthesised is supposed to operate.
If the maximum frequency of the machine (or DUT) is ~2.5GHz, it is supposed to operate at that frequency in the actual environment, but just out of curiosity you can even check operation of DUT with different input clock frequencies by generating different simulations.
Hope it helps!
I have been working on a class project using Verilog. I had to create a circuit and then calculate the power that the circuit uses. I have been trying to do it using Xpower Analyzer I follow the instruction to create the vcd file, compile and synthesize the code using Xilinx ISE 14.7 . Everything goes well until the result shows up. I received 0 power consumption from the clock. I try to constrains the clock and it only give me a increment in dynamic power from 0 to 0.009, but not luck in the clock. Also, I try Xpower in my personal computer and at my university computer lab, so I don't think that it is a software bug.
Moreover, I have try different design such as a simple alu, register etc. Nonetheless, I still getting the same power result.
More information:
Testbench runs well and does what I want
I declare clock like: module toptrafficlight(
clock,rst,output );
List item: I have constrained the clock to 20ns
Timing phase = 0. After synthesis (not sure what this means)
Warrnings from:
HDLCompiler:413 - Line 86: Result of 5-bit expression is truncated to fit in 4-bit target.
PhysDesignRules:372 - Gated clock. Clock net main_gated_clk is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
Power result from Xpower Analyzer
My questions are?
is it a way to setup the clock? which I think might be the cause of the problem
is there anything else needed to be done beside getting the VCD file and synthesize the code?
any other ideas, examples or tutorial?
The screenshot shows that the design is very small, so it's not a big surprise for clock power to be smaller than 1mW. Xilinx also provides an Excel sheet for power estimation. It can be used for a quick tryout to see what circumstances make the clock power significant.
Xilinx Power Estimator (XPE)
I have very poor verilog knowledge, but i need to convert Verilog project, containing some .v files and folders wth .v files to one large EDIF file for parcing.
Is there any easy way to do this?
I have found iverilog tool, but not sure how to convert all project with subfolders at once.
Thank you!
EDIF (Electronic Design Interchange Format) is a vendor-neutral format in which to store Electronic netlists and schematics. https://en.wikipedia.org/wiki/EDIF .
Verilog is a Hardware Description Language, which can describe hardware at a higher, behavioural level of abstraction.
So, in general at least, the two are not compatible. So, in general, you will need to convert your Verilog to gate-level in order for it to be suitable for EDIF. The tool that converts Verilog to gate-level is a logic synthesiser and most, if not all, logic synthesisers will be able to output your netlist as an EDIF file.
So,
if your Verilog is not already gate-level, you will need a logic synthesiser. If you're doing an FPGA design, that will be your FPGA tool: Quartus, Vivado etc.
if your Verilog is already gate-level, then there may be other, more basic, tools that convert from one to another; I don't know. But, if your Verilog is already gate-level, a logic synthesiser will also be able to do the conversion.
Can anyone tell me how to write a verilog code for DWT of an image and download in to fpga.
Actually my project is to write a verilog code to perform discrete wavelet transform of a medical image, can anyone frame the logic or if have the code can you send me, please
I am using xilinx virtex 2 pro..
This one is in VHDL instead of Verilog, but might still provide at least some inspiration.
Generally FPGA's come with software for programming them. Depending on manufacturer those packages are different. But most of FPGA manufacturers(Xilinx, Altera, etc) ship tools to program their chips.
Besides that there are few 3rd party tools:
http://www.synopsys.com/Solutions/EndSolutions/FPGASolution/Pages/default.aspx
http://www.aldec.com/Products/default.aspx
Can anyone tell me how to write a verilog code for DWT of an image and download in to fpga.
Actually my project is to write a verilog code to perform discrete wavelet transform of a medical image, can anyone frame the logic or if have the code can you send me, please
I am using xilinx virtex 2 pro..
This one is in VHDL instead of Verilog, but might still provide at least some inspiration.
Generally FPGA's come with software for programming them. Depending on manufacturer those packages are different. But most of FPGA manufacturers(Xilinx, Altera, etc) ship tools to program their chips.
Besides that there are few 3rd party tools:
http://www.synopsys.com/Solutions/EndSolutions/FPGASolution/Pages/default.aspx
http://www.aldec.com/Products/default.aspx