How to improve the speed of a multiplier in verilog? - verilog

Question

How to improve the speed of a multiplier in verilog?
Hi
I want to know about 'How to improve the speed of a multiplier without increasing clock speed in verilog?'
Does anyone know about regarding this?
We don't have much money to buy DesignWare of Synopsys's.
Unfortunately, Also we met some problem regarding speed limit of multiplier. So I trying to find way to improve multiplier without clock speed up. Especially, our ASIC has already approached to timing limit. We don't have timing margin.But We have to change regarding the multiplier logic.
For example, we have already met the all timing clock in synthesis.but we need to change the algorithm some multiplier regarding logic.

Answer 1

Assuming that all surrounding logic has been minimised, inputs from flip-flops output direct to flip-flops.
module multiplier(
WDITH = 24
)(
input clk,
input signed [WIDTH-1:0] a,
input signed [WIDTH-1:0] b,
output logic signed [(WIDTH*2) -1:0] mul
);
logic signed [WIDTH-1:0] a_i;
logic signed [WIDTH-1:0] b_i;
always #(posedge clk) begin
a_i <= a;
b_i <= b;
mul <= a_i * b_i;
end
endmodule
Having the a*b style in RTL allows the synthesis library to choose the best multiplier style (Area/power vs speed ). Assuming the question is a result of synthesis not being able to close timing.
What limits the multiplier speed?
Input width could be minimised to speed up design.
For ASIC design the next process node could be chosen ie going from 22nm to 14nm. For FPGA a more expensive chip supporting a faster multiplier speed.
Alternatively the target clock speed of the Multiplier could be halved and two used in parallel. Multi-cycle clocks could be used in synthesis if actual clock is to remain the same but the result sampled every other clock.
module multiplier(
WDITH = 24
)(
input clk,
input rst_n,
input signed [WIDTH-1:0] a,
input signed [WIDTH-1:0] b,
output logic signed [(WIDTH*2) -1:0] mul
);
logic signed [WIDTH-1:0] a1_i;
logic signed [WIDTH-1:0] b1_i;
logic signed [WIDTH-1:0] a2_i;
logic signed [WIDTH-1:0] b2_i;
logic signed [(WIDTH*2) -1:0] mul1;
logic signed [(WIDTH*2) -1:0] mul2;
logic state;
always #(posedge clk, negedge rst_n) begin
if (~rst_n) begin
state <= 'b0;
end
else begin
state <= ~state;
end
end
always #* begin
mul1_i = a1_i * b1_i;
mul2_i = a2_i * b2_i;
end
always #(posedge clk, negedge rst_n) begin
if (~rst_n) begin
a1_i <= 'b0;
b1_i <= 'b0;
a2_i <= 'b0;
b2_i <= 'b0;
mul <= 'b0
end
else begin
if (state) begin
a1_i <= a;
b1_i <= b;
mul <= mul2_i;
end
else begin
a2_i <= a;
b2_i <= b;
mul <= mul1_i;
end
end
end
endmodule
Where mul1_i and mul2_i; are given multi cycle properties in synthesis, so they have twice the clock period to resolve.
Another possibility is to instantiate a multi-cycle design ware multiplier, using the designware Datapath and building block IP. They have 2,3,4,5 and 6 cycle multipliers.
An example of a 2-Stage Multiplier :
module DW02_mult_2_stage_inst( inst_A, inst_B, inst_TC,
inst_CLK, PRODUCT_inst );
parameter A_width = 8;
parameter B_width = 8;
input [A_width-1 : 0] inst_A;
input [B_width-1 : 0] inst_B;
input inst_TC;
input inst_CLK;
output [A_width+B_width-1 : 0] PRODUCT_inst;
// Instance of DW02_mult_2_stage
DW02_mult_2_stage #(A_width, B_width)
U1 ( .A(inst_A), .B(inst_B), .TC(inst_TC),
.CLK(inst_CLK), .PRODUCT(PRODUCT_inst) );
endmodule