I'm having a lot of trouble making any sort of sense of this problem. I'm supposed to create a module for an 8 bit wide 2-to-1 multiplexer using Verilog.
The question:
Write a verilog module that uses 8 assignment statements to describe the circuit. Use SW[17] on the DE2 board as the s input, switches [7:0] as the X input, switches [15:8] as the Y input. Connect SW switches to the red lights LEDR and output M to the green light LEDG [7:0].
My code:
module example(M, X, Y, S)
input[15:0] SW;
input SW[17];
output [7:0] LEDR;
output [7:0] LEDG;
output [7:0] M;
wire [7:0] X = SW[7:0];
wire [7:0] Y = SW[15:8];
wire S = SW[17]
assign M[0] = X[0] & ~S | Y[8] & S;
assign M[1] = X[1] & ~S | Y[9] & S;
assign M[2] = X[2] & ~S | Y[10] & S;
assign M[3] = X[3] & ~S | Y[11] & S;
assign M[4] = X[4] & ~S | Y[12] & S;
assign M[5] = X[5] & ~S | Y[13] & S;
assign M[6] = X[6] & ~S | Y[14] & S;
assign M[7] = X[7] & ~S | Y[15] & S;
endmodule
I don't understand how I'm supposed to assign m to the green LEDG[7:0] since I've already assigned each M to those conditional statements. Anyone know how to get around this?
While there are multiple ways to do this, I suggest make a wrapper module containing the board i/o as inputs and outputs and instantiate your MUX inside of it:
module top(input [17:0] SW,
output [15:0] LEDR,
output [7:0] LEDG);
example ex(.M(LEDG), .s(SW[17]), .X(SW[7:0]), .Y(SW[15:8]));
assign LEDR[7:0] = X;
assign LEDR[15:8] = Y;
endmodule
[insert your mux module minus the board i/o here]
If you cannot use the above solution, you can look up how to use the Pin Planner in QuartusII (which I assume you are using from the DE2 reference in your prompt).
Related
DO I need anything else to make a 16bit CLA ??????
so far I instantiated 4 (4 bit CLA to make a 16 bit CLA)
but I think I am missing about the carry I just don't understand how to add it to what I have since the 8 bit CLA was just instantiating 2 (4 bit CLA) I don't understand why can't just instantiate 4 (4 bit CLA together to get 16 bit CLA). Can someone help me figure out how to complete the 16bit CLA?
//CLA16Top.sv
module CLA4Bit(ain, bin, cin, sum, cout);
timeunit 1ns/1ns;
input [3:0] ain,bin;
input cin;
output logic [3:0] sum;
output logic cout;
logic [3:0] G,P,C;
// Carry propagate
assign P = ain ^ bin;
//Carry generate
assign G = ain & bin;
// Calculating each stage of the carry out
assign C[0] = cin;
assign #4 C[1] = (G[0] | (C[0] & P[0]));
assign #6 C[2] = (G[1] | (G[0] & P[1]) | (C[0] & P[1] & P[0]));
assign #8 C[3] = (G[2] | (G[1] & P[2]) | (G[0] & P[1] & P[2]) | (C[0] &
P[2] & P[1] & P[0]));
assign sum = P ^ C;
assign #13 cout= (G[3] | (G[2]&P[3]) | (G[1]&P[2]&P[3]) |
(G[0]&P[1]&P[2]&P[3]) | (C[0]&P[0]&P[1]&P[2]&P[3]));
endmodule
/*
module CLA16Top;
timeunit 1ns/1ns;
parameter nBITS = 16;
logic [nBITS - 1 : 0] ain, bin, sum;
logic in;
logic cout;
logic c4, c8, c12, c16;
assign cout = c16;
// instantiating the 16 bit CLA
CLA4Bit uut1(
.ain(ain[3:0]),
.bin(bin[3:0]),
.cin(cin),
.sum(sum[3:0]),
.cout(c4)
);
CLA4Bit uut2(
.ain(ain[7:4]),
.bin(bin[7:4]),
.cin(c4),
.sum(sum[7:4]),
.cout(c8)
);
CLA4Bit uut3(
.ain(ain[11:8]),
.bin(bin[11:8]),
.cin(c8),
.sum(sum[11:8]),
.cout(c12)
);
CLA4Bit uut4(
.ain(ain[15:12]),
.bin(bin[15:12]),
.cin(c12),
.sum(sum[15:12]),
.cout(c16)
);
// SIMULATE (CLA16Top)
//
test #(16) TB(.*);
endmodule: CLA16Top
I get compile errors in your test module. Change:
output in;
to:
output cin;
Also, the double-quoted string must be on one line:
$display("For inputs: ain = %b, bin = %b, cin = %b :: Actual outputs: cout = %1b, sum = %b :: Expected outputs: cout = %1b, sum = %b", ain, bin, cin, cout,
test_count could be too big to fit into an int variable. Use real and %g:
real test_count;
$display("***Congratulations, No errors found after %g tests***", test_count);
After those changes, the code compiles and runs for me. It took about 2 hours before the nested loops completed, and only the final message displays:
***Congratulations, No errors found after 8.58993e+09 tests***
This indicates that the adder works properly.
If you want to see more intermediate results, add more displays in the loops.
Note: The test module code was removed from the Question after I posted this Answer.
I'm new to Verilog programming. I'm trying to put together an 8-bit Carry Lookahead Adder as a step toward building a 64-bit CLA. Basically, the way I implemented it is I use 2 4-bit CLA "blocks" to create the 8-bit CLA. I'll provide my code, then an explanation of the problem I'm having.
Code below:
// 4-BIT CLA CODE
module CLA4Bit(A, B, carryIn, carryOut, PG, GG, Sum);
input[3:0] A, B;
input carryIn;
output carryOut;
output PG;
output GG;
output[3:0] Sum;
wire[3:0] G, P, C;
assign G = A & B;
assign P = A ^ B;
assign Sum = P ^ C;
assign C[0] = carryIn;
assign C[1] = G[0] | (P[0] & C[0]);
assign C[2] = G[1] | (P[1] & G[0]) | (P[1] & P[0] & C[0]);
assign C[3] = G[2] | (P[2] & G[1]) | (P[2] & P[1] & G[0]) | (P[2] & P[1] & P[0] & C[0]);
assign PG = P[3] & P[2] & P[1] & P[0];
assign GG = G[3] | (P[3] & G[2]) | (P[3] & P[2] & G[1]) | (P[3] & P[2] & P[1] & G[0]);
endmodule
// 8-BIT CLA CODE BELOW
module CLA8Bit(A, B, carryIn, carryOut, Sum);
// 8-bit wire for the inputs A and B
input[7:0] A, B;
// Wire for the ORIGINAL carry-in
input carryIn;
// Wire for the carryOut
output carryOut;
// Wire that carries the Sum of this CLA
output[7:0] Sum;
// Wires for the propagate of the first 4-bit block (p3)
// and the second (p7)
wire p3, p7;
// Wires for the generate of the first 4-bit block (g3)
// and the second (g7)
wire g3, g7;
// Wires for the carry of the first block (c3) and the
// second (c7)
wire c3, c7;
// The two 4-bit CLA blocks that make up the 8-bit CLA
CLA4Bit block1(A[3:0], B[3:0], carryIn, c3, p3, g3, Sum[3:0]);
CLA4Bit block2(A[7:4], B[7:4], c3, c7, p7, g7, Sum[7:4]);
endmodule
I wrote a basic testbench to test my code:
module CLA_TB();
// TEST THE 8-BIT CLA
// Inputs
reg[7:0] A;
reg[7:0] B;
reg carryIn;
// Outputs
wire carryOut;
wire[7:0] Sum;
wire PG;
wire GG;
// Instantiate the 8-bit CLA
CLA8Bit CLA8BitDUT (
.A(A),
.B(B),
.carryIn(carryIn),
.carryOut(carryOut),
.Sum(Sum)
);
// Initialize the testbench signals
initial
begin
// Start with the carryIn set to 0
assign carryIn = 0;
// The standard first test. Set
// A = b0000 0001 and B = b0000 0001
// Answer should be Sum = b0000 0010
assign A = 8'b00000001;
assign B = 8'b00000001;
#20
// Next, set A = b0001 1011 and
// B = b1101 0111. Answer should
// be Sum = b1111 0010 = hF2.
assign A = 8'b00011011;
assign B = 8'b11010111;
#20
// Finally, try setting the carryIn
// to 1 and then test A = b0111 1011
// and B = b1101 0011. Answer should be
// Sum = 0100 1111 w/ overflow carry
assign carryIn = 1'b1;
assign A = 8'b01111011;
assign B = 8'b11010011;
#20
$finish;
end
endmodule
So the problem is, in my simulations of the testbench (I use ModelSim), the first 4 bits of the Sum (which correspond to the first 4-bit CLA instance in the 8-bit CLA module) are given as X in the Wave page. The second 4 bits add just fine, though.
After doing some research, I found out that X's are displayed in Verilog when a wire has more than one driver (source of the signal?). However, I don't see any place where I send more than one signal to my first 4-Bit CLA instance in the 8-Bit CLA module. Also, if something like that were the cause, then I don't know why it wouldn't happen to the second set of 4 bits as well, since both the 4-bit CLAs are set up very similarly.
Why is this happening?
X's are displayed in Verilog when a wire has more than one driver
That is true but it is only part of the story. There are other cases which produce X'es:
If a reg is not given a value it will be X.
If a Z is used in an expression it will produce an X .
Your waveform has some obvious 'Z' (blue) lines one it.
If you following the signals back to where they originate: your 4-bit adder never assigns a value to carryOut.
Then you make the same error in CLA8Bit.
If you see a 'Z' in a simulation: jump on it! 99.9% of the time you have an wire which has not been given a value!
I'm trying to implement in hardware (using Verilog) the function described by this pseudo code:
if A then
output [63:0] = b[63:56], c[X-1:0], b[Y-1:0]
else output [63:0] = c[X-1:0], b[Y-1:0]
A is a boolean value, while output, b and c are 64 bits long.
X and Y change at runtime so they can't be Verilog variables.
The value of X changes with A:
if A then
X = 56 - Y
else X = 63 - Y
while Y is read from a 6 bit register so it can be any number from 0 to 63.
So for both cases of A all 64 bits of output will be assigned.
I know bit masking and mux selection with A is required but it is a bit complex and I can't quite get a clear picture on how to implement this in Verilog.
The runtime dependent bit selection can be implemented with shift(<<), variable bit selection(a[k+:8]), a smartly designed for loop(a[i] = condition ? b:c) or a completely expressed case. And all of them should have similar synthesis result. Based on experience, the case implementation should have best area performance.
Here is an example (with testbench) for shift implementation:
`timescale 1ns/1ps
module example(
input A,
input [5:0] Y,
input [63:0] b, c,
output [63:0] result
);
reg [63:0] o_a, o_abar;
assign result = A ? o_a : o_abar;
wire [5:0] X = A ? (56-Y) : (63-Y);
reg [63:0] c1_tmp, b1_tmp, mask;
always#(*)begin
c1_tmp = (c << Y) & {8'd0, {56{1'b1}}};
mask = (({64{1'b1}}>>X) << Y) | ({64{1'b1}} >> (64-Y));
b1_tmp = mask & b;
o_a = c1_tmp | b1_tmp;
end
reg [63:0] c2_tmp, b2_tmp;
always#(*)begin
c2_tmp = c << Y;
b2_tmp = b & ({64{1'b1}} >> Y);
o_abar = c2_tmp | b2_tmp;
end
endmodule
module test;
reg A;
reg [5:0] Y;
reg [63:0] b, c;
wire [63:0] result;
example ex(.A(A), .Y(Y), .b(b), .c(c), .result(result));
initial begin
A = 1;
Y = 6;
c = -1;
b = 0;
#10
$display("%b", result);
$finish;
end
endmodule
Can anyone see any blatant errors as to why this does not compile. I think the logic is correct for most of these operations. Its most likely syntax errors.
the only thing i can think of is the switch statement isn't written correctly as well as the add module. Each of the foury bit statements are connected to one of the modules below it. (bitwise not binary)
module _4bitALU(C , O , A , B , Switch);
input[3:0] A ;
input [3:0] B;
input [3:0] Switch;
output [3:0] O;
output C;
case(Switch)
4'B0000: notop(O , A);
4'B0001: andop(O , A , B);
4'B0010: orop(O , A , B);
4'B0011: xorop(O , A , B);
4'B1000: addop(C , O , A , B);
endcase // case (Switch)
endmodule // _4bitALU
module notop(O , A);
input [3:0] A;
output [3:0] O;
assign O = ~A;
endmodule // notop
module andop(O , A , B);
input [3:0] A;
input [3:0] B;
output [3:0] O;
assign O = (A & B);
endmodule // andop
module orop(O , A , B);
input [3:0] A;
input [3:0] B;
output [3:0] O;
assign O = (A | B);
endmodule // orop
module xorop(O , A , B);
input [3:0] A;
input [3:0] B;
output [3:0] O ;
assign O = (A ^ B);
endmodule // xorop
module addop(C , O , A , B);
input [3:0] A;
input [3:0] B;
output [3:0] O;
output C;
assign C1 = (A[0] & B[0]);
assign C2 = ((A[1] & B[1]) | (A[1] & C1) | (B[1] & C1));
assign C3 = ((A[2] & B[2]) | (A[2] & C2) | (B[2] & C2));
assign C = ((A[3] & B[3]) | (A[3] & C3) | (B[3] & C3));
assign O[0] = (A[0] ^ B[0]);
assign O[1] = ((A[1] ^ B[1] ^ C1) | (A[1] & B[1] & C[1]));
assign O[2] = ((A[2] ^ B[2] ^ C2) | (A[2] & B[2] & C[2]));
assign O[3] = ((A[3] ^ B[3] ^ C3) | (A[3] & B[3] & C[3]));
assign O[4] = ((A[4] ^ B[4] ^ C4) | (A[4] & B[4] & C[4]));
endmodule // addop
There are quite a few problems in the _4bitALU module:
The case statement is not inside an always block.
You can't "call" other modules like you do in the case branches, instead you need to create instances of those modules and assign the wires which connect to those instances within the case branches to the desired output(s).
These issues are rather basic Verilog, therefore I suggest you read up on how it is used (maybe this tutorial might help). Remember that you are (in most cases anyway) trying to describe the structure of hardware, not a software program that just gets executed.
I have a 8-bit ALU unit in verilog that can do addition, invert, etc. This single unit is tested and performs correctly. When I combine 4 of these to make a bigger ALU every output is correct except when I choose the addition operation it comes out as
xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx01010101, basically the first alu does the work right then the output from the second is xxxxxxxx as is the third and fourth. This is really frustrating!!
the 8 bit module( it would be nice to point if this model is behavioral or structural model i go for the former!)
module alu_8bit(
output reg [7:0] out,
output reg cout,g,e,
input [7:0] A,B,
input cin,
input [2:0] S
);
//used functions
parameter BUF_A = 3'b000;
parameter NOT_A = 3'b001;
parameter ADD = 3'b010;
parameter OR = 3'b011;
parameter AND = 3'b100;
parameter NOT_B = 3'b101;
parameter BUF_B = 3'b110;
parameter LOW = 3'b111;
always #(A or B or S) begin
//Comparator
g = A>B;
e = A==B;
//Other selective functions
case(S)
BUF_A: out = A;
NOT_A: out = ~A;
ADD: {cout,out} = A+B+cin;
OR: out = A | B;
AND: out = A & B;
NOT_B: out = ~B;
BUF_B: out = B;
LOW: out = {8{1'b0}};
endcase
end
endmodule
Here is the code of the bigger one:
module alu_32bit(
output [31:0] out,
output cout,g,e,
input [31:0] A,B,
input cin,
input [2:0] S
);
wire e1,e2,e3,e4;
wire g1,g2,g3,g4;
alu_8bit ALU1(out[7:0],cin2,g1,e1,A[7:0],B[7:0],cin,S);
alu_8bit ALU2(out[15:8],cin3,g2,e2,A[15:8],B[15:8],cin2,S);
alu_8bit ALU3(out[23:16],cin4,g3,e3,A[23:16],B[23:16],cin3,S);
alu_8bit ALU4(out[31:24],cout,g4,e4,A[31:24],B[31:24],cin4,S);
assign g = g4 | (e4 & g3) |(e4 & e3 & g2) | (e4& e3 & e2 & g1);
assign e = e4 & e3 & e2 & e1;
endmodule
Can any one give some help?! if you need more info just tell me.
Edited:
Waveform pic clearly input comes in correct but output not
The dataflow diagram shows that ALU1 output is just fine
Your sensitivity list for the main part of the ALU doesn't include cin.