comparing t_data and rx_data for errors and giving the error value by total_error "verilog" - verilog

Question

I have made a bit error rate (ber) file in verilog. In ber module, I have made total_error which compares the t_data and rx_data and totals up the number of errors it gets from comparing.
Here is the code
`timescale 1ns / 1ps
module ber
(
clk,
rstn,
T_Data,
RX_Data,
total_error,
enable
);
//inputs
input clk;
input rstn;
input [15 : 0] T_Data;
input [15 : 0] RX_Data;
input enable;
//outputs
output [15:0] total_error;
reg [4:0] i;
reg [15:0] subtotal, next_subtotal;
assign total_error = subtotal;
always #(posedge clk) begin : comb
next_subtotal = 0;
for (i = 0; i < 16; i = i + 1)
begin
if (T_Data[i] != RX_Data[i] )
begin
next_subtotal = next_subtotal + 1;
end
end
end
always #(posedge clk) begin : dff
if (rstn==1'b0)
begin
subtotal <= 7'b0000000;
end else
begin
subtotal <= next_subtotal;
end
end
endmodule
After making the BER file, I made another file known as BER_STATE_MACHINE where I made a state machine for TRANFERRING AND RECEIVING SIGNALS, I instantiated the ber file with this ber_state_machine file.
Here is the code
// --------------------------------------------------------------------
`timescale 1ns/1ps
module ber_state_machine
(
clk,
resetn,
T_Data [15:0],
T_Valid,
T_Ready,
RX_Data [15:0],
RX_Active,
RX_Valid,
total_error
);
//-----------------------------------
input resetn, clk;
// DECLARING INPUTS AND OUTPUTS FOR TRASMIT SIGNALS
input [15 : 0] T_Data;
input T_Valid;
output T_Ready;
// DECLARING INPUTS AND OUTPUTS FOR RECEIVING SIGNALS
input [15 : 0] RX_Data;
input RX_Active;
input RX_Valid;
//-----------------------------------
output [15 : 0] total_error;
//-----------------------------------
reg [6:0] sel;
reg execute_in;
reg T_Ready;
//------------------------------------------
ber uut
(
.clk(clk),
.rstn(resetn),
.T_Data(T_Data),
.RX_Data(RX_Data),
.total_error(total_error),
.enable(execute_in)
);
//------------------------------------------
// MAKING STATE MACHINE HERE //INPUTS
always # (posedge clk or negedge resetn) // state machine for changing states
begin
if (resetn == 1'b1) // idle state
begin
sel <= 7'b000; // state 0
end
else if (T_Valid == 7'b1)
begin
sel <= 7'b001; // state 1
end
else if (sel == 7'b001)
begin
sel <= 7'b010; // state 2
end
else if (RX_Active == 7'b1)
begin
sel <= 7'b011; // state 3
end
else if (T_Valid == 7'b1 && RX_Valid == 7'b1)
begin
sel <= 7'b100; // state 4
end
else if (sel == 7'b100)
begin
sel <= 7'b101; // state 5
end
else if (T_Valid == 2'b0 && RX_Valid == 2'b0)
begin
sel <= 7'b100; // going back to state 4
end
end
// STATE MACHINE //OUTPUTS
always # (posedge clk) // outputs for every state in state diagram
begin
case(sel)
7'b000 :
execute_in = 2'b0; // state 0
7'b001 :
T_Ready = 2'b1; // state 1
7'b010 :
T_Ready = 2'b0; // state 2
7'b011 :
execute_in = 2'b1; // state 3
7'b100 :
T_Ready = 2'b1; // state 4
7'b101 :
T_Ready = 2'b0; // state 5
endcase
end
endmodule
After this, I made a test bech to see the behavioral simulation.
There are few problems that I am getting which I am not able to fix due to less verilog experience.
the t_data and rx_data are undefined in the simulation, after the last bit, I can see the value each contains but from 0 - 15, they are undefined. I really dont know whats the problem.
I dont see any value in total_error, even though I put errors in t_data and rx_data but I dont see the number of errors in total_error. But I can observe in the simulation that there are errors in t_data and rx_data in their final values.
Here is the code for test bench
`timescale 1ns / 1ps
module test_bench();
//inputs
reg execute_in;
reg clk;
reg resetn;
//inputs for transferring signals
reg [15:0] T_Data;
reg T_Valid;
//inputs for receiving signals
reg [15:0] RX_Data;
reg RX_Active;
reg RX_Valid;
//outputs
wire [15:0] total_error;
wire T_Ready;
//instantiate the unit under test (UUT)
ber_state_machine uut_ber
(
.clk(clk),
.resetn(resetn),
.T_Data(T_Data),
.T_Valid(T_Valid),
.T_Ready(T_Ready),
.RX_Data(RX_Data),
.RX_Active(RX_Active),
.RX_Valid(RX_Valid),
.total_error(total_error)
);
initial begin
clk = 1'b0;
resetn = 1'b1;
repeat(4) #10 clk = ~clk;
resetn = 1'b0;
forever #10 clk = ~clk;
end
initial begin
#100
execute_in = 0;
#100
execute_in = 1;
#100
T_Valid = 1'b0;
RX_Active = 1'b0;
#100
RX_Valid = 1'b0;
//************//
#100
RX_Active = 1'b1;
T_Valid = 1'b1;
T_Data[0] = 1'b0; // data 0 // make it 0 for error
RX_Valid = 1'b1;
RX_Data[0] = 1'b1; // make it 0 for error
#50
T_Valid = 1'b0;
//************//
#100
RX_Active = 1'b1;
T_Valid = 1'b1;
T_Data[1] = 1'b1; // data 1
RX_Valid = 1'b1;
RX_Data[1] = 1'b1; // make it 0 for error
#50
T_Valid = 1'b0;
#100
RX_Active = 1'b1;
T_Valid = 1'b1;
T_Data[2] = 1'b1; // data 2
RX_Valid = 1'b1;
RX_Data[2] = 1'b1; // make it 0 for error
#50
T_Valid = 1'b0;
#100
RX_Active = 1'b1;
T_Valid = 1'b1;
T_Data[3] = 1'b0; // data 3
RX_Valid = 1'b1;
RX_Data[3] = 1'b1; // make it 0 for error
#50
T_Valid = 1'b0;
#100
RX_Active = 1'b1;
T_Valid = 1'b1;
T_Data[4] = 1'b1; // data 4
RX_Valid = 1'b1;
RX_Data[4] = 1'b1; // make it 0 for error
#50
T_Valid = 1'b0;
#100
RX_Active = 1'b1;
T_Valid = 1'b1;
T_Data[5] = 1'b1; // data 5
RX_Valid = 1'b1;
RX_Data[5] = 1'b1; // make it 0 for error
#50
T_Valid = 1'b0;
#100
RX_Active = 1'b1;
T_Valid = 1'b1;
T_Data[6] = 1'b1; // data 6
RX_Valid = 1'b1;
RX_Data[6] = 1'b1; // make it 0 for error
#50
T_Valid = 1'b0;
#100
RX_Active = 1'b1;
T_Valid = 1'b1;
T_Data[7] = 1'b1; // data 7
RX_Valid = 1'b1;
RX_Data[7] = 1'b1; // make it 0 for error
#50
T_Valid = 1'b0;
#100
RX_Active = 1'b1;
T_Valid = 1'b1;
T_Data[8] = 1'b1; // data 8
RX_Valid = 1'b1;
RX_Data[8] = 1'b0; // make it 0 for error
#50
T_Valid = 1'b0;
#100
RX_Active = 1'b1;
T_Valid = 1'b1;
T_Data[9] = 1'b1; // data 9
RX_Valid = 1'b1;
RX_Data[9] = 1'b1; // make it 0 for error
#50
T_Valid = 1'b0;
#100
RX_Active = 1'b1;
T_Valid = 1'b1;
T_Data[10] = 1'b1; // data 10
RX_Valid = 1'b1;
RX_Data[10] = 1'b1; // make it 0 for error
#50
T_Valid = 1'b0;
#100
RX_Active = 1'b1;
T_Valid = 1'b1;
T_Data[11] = 1'b1; // data 11
RX_Valid = 1'b1;
RX_Data[11] = 1'b1; // make it 0 for error
#50
T_Valid = 1'b0;
#100
RX_Active = 1'b1;
T_Valid = 1'b1;
T_Data[12] = 1'b1; // data 12
RX_Valid = 1'b1;
RX_Data[12] = 1'b1; // make it 0 for error
#50
T_Valid = 1'b0;
#100
RX_Active = 1'b1;
T_Valid = 1'b1;
T_Data[13] = 1'b1; // data 13
RX_Valid = 1'b1;
RX_Data[13] = 1'b1; // make it 0 for error
#50
T_Valid = 1'b0;
#100
RX_Active = 1'b1;
T_Valid = 1'b1;
T_Data[14] = 1'b1; // data 14
RX_Valid = 1'b1;
RX_Data[14] = 1'b1; // make it 0 for error
#50
T_Valid = 1'b0;
#100
RX_Active = 1'b1;
T_Valid = 1'b1;
T_Data[15] = 1'b1; // data 15
RX_Valid = 1'b1;
RX_Data[15] = 1'b1; // make it 0 for error
#50
T_Valid = 1'b0;
end
endmodule
Please help me out in this

Answer 1

Your logic uses an active-low reset. However, your testbench starts with the reset signal de-asserted (resetn=1), then asserts it (resetn=0) after 40ns. I think you need to invert the polarity in the testbench:
initial begin
clk = 1'b0;
resetn = 0; // Assert active-low reset
repeat(4) #10 clk = ~clk;
resetn = ~resetn; // De-assert reset
forever #10 clk = ~clk;
end