The following set of codes do the same thing.Is there any difference between them ?If not , why is wait (clk) not generally used?
always #(posedge clk)
begin
end
always wait(clk)
begin
end
#(posedge clk) is edge sensitive , hence it is used to model synchronous circuits.While, wait(clk) is level sensitive.Since most circuits are designed to be synchronous #(posedge clk) is predominantly used
wait (expression)
The "expression" is evaluated, if false, then execution is suspended until the expression becomes true. If the expression is true when the statement is reached, then the wait has no effect, and execution proceeds to the controlled statement.
#(posedge clk) - is an edge event.
posedge:0,x,z->1 negedge:1,x,z->0
Edge events are useful for modelling clocked logic elements, like flip-flops. They are also useful for synchronizing activity in a model based on a common clock. Example, in the following always block,it enters the always block on the negative edge of clock.
always #(negedge clock)
x = f(y);
Related
I'm trying to add an edge_triggered reset to my module, meaning that only if a transient from 0 to 1 detected in reset, the reset operation should be perform.
and further more, I don't want to use any initial block in my module (because I think initial blocks have issues in FPGAs).
finally, I decided to following something like this:
always # (posedge clock, posedge reset) ...
but the problem I encountered, is that I need to know which element of always block sensitivity list is activated.
also I think this method isn't a proper solution:
always # (posedge clock, posedge reset) begin
if(reset) begin
//doing reset operations
end
.
.
.
end
because if reset is 1 from previous clocks (not transient from 0 to 1) in next posedge clock the reset operation will be perform! but we didn't want this.
so, is there any way to find out which element of sensitivity list activated the always block?
or even any other solution for implementing edge_triggered reset?
There almost certainly isn't a primitive in your FPGA that will do exactly what you want. And even in simulation, you wouldn't be able to tell which of the edges in the sensitivity list triggered the update.
The code you posted should synthesize, but as you noted it will behave like a standard asynchronous reset and continue to reset as long as reset is high. In order to reset only on the reset rising edge, you'll need some clock domain crossing logic to detect the edge and output a single pulse on the clock domain.
For example:
// This module can assert reset_pulse asynchronously but must output a pulse
// for at least one 'clock' cycle and deassert synchronously.
async_edge_to_pulse e2p (
.in_edge (reset),
.out_clock (clock),
.out_pulse (reset_pulse)
);
always #(posedge clock or posedge reset_pulse) begin
if (reset_pulse) begin
// reset logic
end else begin
// operational logic
end
end
i know high level async reset can be achieved like:
always#(posedge clk or posedge rst)
begin
if (rst==1)
but how to realize posedge async reset, which means the moment reset edge coming up, the logic in always block reset immediately?
i wrote the logic below:
always#(posedge clk or posedge rst)
begin
rst_pre<=rst;
if(!rst_pre && rst) // to test if rst is posedge
//execute reset logic here...
but the question is, the always block was triggered in a unexpected high frequency, i finally figured out that although there was only 1 posedge of rst, the always block was triggered by rst signal much more than 1 time.
(tested using altera cyclone 10LP with quartus 18)
I think the method i used to achieve posedge async reset is not stable, can anyone tell me what can i do to solve this?
What you are trying to achieve is a asynchronous reset. It can be posedge or negedge.
always#(posedge clk or posedge rst)
begin
if (rst)
// do the reset
else begin
// your normal execution logic
end
end
If you want to use negedge reset then you can use:
always#(posedge clk or negedge rst)
begin
if (~rst)
// do the reset
else begin
// your normal execution logic
end
end
Other than that, there is nothing complicated on reset. Both on these occasions, on posedge/negedge of rst, block will get triggered and it will do the reset.
The very first code snippet which you call "high level async reset" logic is "posedge asynchronous reset logic".
The code snippet specified a active high asynchronous reset signal rst. "active high" + "asynchronous" means signals generated by this always block are reset immediately when rst asserts.
As soon as you include "posedge/negedge reset" in the sensitivy list, and the reset condition inside the always block has priority over the rest of the sequential logic, it is asynchronous:
always # (posedge clk_i, posedge arst_i) begin
if(arst_i) begin
...this condition has to be first
end
else begin
...normal sequential logic
end
end
Use "posedge" for active-high reset, and "negedge" for active-low reset.
Extra note: Sometimes it is also useful to have a reset synchronizer. This synchronized "soft reset" should be included in the normal sequential logic and it would help to have everything synchronized with the clock. By doing this you would have a first asynchronous reset condition, and the last synchronized reset would avoid any metastabiliy problems regarding the asynchronous condition.
I am wondering about the behavior of the below code. There are two always blocks, one is combinational to calculate the next_state signal, the other is sequential which will perform some logic and determine whether or not to shutdown the system. It does this by setting the shutdown_now signal high and then calling state <= next_state.
My question is if the conditions become true that the shutdown_now signal is set (during clock cycle n) in a blocking manner before the state <= next_state line, will the state during clock cycle n+1 be SHUTDOWN or RUNNING? In other words, does the shutdown_now = 1'b1 line block across both state machines since the state signal is dependent on it through the next_state determination?
enum {IDLE, RUNNING, SHUTDOWN} state, next_state;
logic shutdown_now;
// State machine (combinational)
always_comb begin
case (state)
IDLE: next_state <= RUNNING;
RUNNING: next_state <= shutdown_now ? SHUTDOWN : RUNNING;
SHUTDOWN: next_state <= SHUTDOWN;
default: next_state <= SHUTDOWN;
endcase
end
// Sequential Behavior
always_ff # (posedge clk) begin
// Some code here
if (/*some condition*/) begin
shutdown_now = 1'b0;
end else begin
shutdown_now = 1'b1;
end
state <= next_state;
end
First off, you are not following property coding. The always_comb should only use blocking (=) assignments, never non-blocking (<=). And always_ff is the reverse, only non-blocking (<=) assignments, never blocking (=).
With the code as is, state will go RUNNING. This is because the assignment to next_state is non-blocking and thereby next_state will not be updated until later in the scheduler.
Hypothetically, if next_state and shutdown_now were both blocking assignments, then the simulator will have a race condition. Both next_state could be evaluated and updated before or after state is evaluated. This is why it is not a good idea to mix blocking and non-blocking in the same always block.
If properly coded, ie next_state = ... and shutdown_now <= ..., then state will also go to RUNNING. This is because shutdown_now update happens after all scheduled evaluations are complete. So next_state will not see the 1'b1 until after state is evaluated.
Miles, you really only have one state machine, that's the code in your always_comb block. The always_ff just creates a register to hold your state.
The way your code is written now, you will perform a shutdown in the following sequence:
cycle n: the logic in your always_ff block will determine if a shutdown should happen, and will SCHEDULE the shutdown_now signal to assert in the next clock tick.
cycle n+1: shutdown_now asserts, and the state machine (currently in RUNNING) will set the next_state to SHUTDOWN.
cycle n+2: now your state machine will be in the SHUTDOWN state.
Not sure that you need to have your shutdown logic in an always_ff block. If you move that code to a always_comb block, you could leave the rest of your code the same and your state machine would move to the SHUTDOWN state in cycle n+1.
Here is how I would expect that code to perform:
You have two registers: a "shutdown_now" register and a "state" register.
On posedge of clk, the state of both of these registers is updated atomically. That is: when a blocking assignment to shutdown_now takes place, the current process isn't interrupted while state_next gets updated. Instead, for the purposes of the always_ff process, state_next is whatever value it held at the beginning of the posedge clk simulation "tick."
So:
on the first posedge clock tick: shutdown_now will switch from 0 to 1.
Once the "posedge clk" process has completed, the "always_comb" block will notice that it has work to do, and will update state_next (ie. a combinational decode from the new state of the 2 registers).
on the second posedge clock tick: state gets latched with the updated state_next.
So, it will take 2 cycles to shut down your system, not 1.
i just want to know the difference between this two statement
always #(posedge CLK)
begin
state <= next_state;
end
AND:
always #(CLK)
begin
case(CLK)
1'b1:
state <= next_state;
1'b0:
state <= state;
end
Is there a difference between both ?
Thanks
Not quite. posedge detects these transitions (from the LRM):
Table 43—Detecting posedge and negedge
To 0 1 x z
From
0 No edge posedge posedge posedge
1 negedge No edge negedge negedge
x negedge posedge No edge No edge
z negedge posedge No edge No edge
So, 0->x is a posedge, for example. Your second example only detects cases where CLK ends up as 1, so misses 0->x and 0->z.
The IEEE Std. 1364.1(E):2002 (IEC 624142(E):2005), the Verilog register transfer level synthesis standard, states in Sec. 5.1 that an always block without any posedge/negedge events in the sensitivity list is combinational logic. I.e. the signals in the event list are ignored and the block is synthesized as if an implicit expression list (#(*), #*) was used. The following example is given in the standard ("Example 4" on page 14):
always # (in)
if (ena)
out = in;
else
out = 1’b1;
// Supported, but simulation mismatch might occur.
// To assure the simulation will match the synthesized logic, add ena
// to the event list so the event list reads: always # (in or ena)
(the comment is also copied from the standard document)
I.e. for a synthesis tool your second block is effectively:
always #*
begin
case(CLK)
1'b1:
state <= next_state;
1'b0:
state <= state;
end
which is just a multiplexer with CLK as select input, next_state as active-1 input and the output (state) fed back as active-0 input. A smart synthesis tool might detect that this is identical to a d-type latch with CLK as enable-input and create a d-type latch instead of a combinational loop. Note that the synthesis tool is not required to detect this latch because the code explicitly assigns state in all branches (compare Sec. 5.3. of the standard).
Either way this is different from the d-type flip-flop your first code example would synthesize to. This is one of many cases where Verilog-code has different meaning in simulation and synthesis. Therefore it is important to (1) write synthesizeable Verilog code in a way that avoids this cases and (2) always run post-synthesis simulations of your design (even if you are also using formal verification!) to make sure you have successfully avoided this pitfalls.
Functionally, those two circuits describe the same behavior in verilog, so I think there should be no difference.
However you should generally use the first style, as that is the one that is standard for writing synthesizable code, and most understandable by anyone else reading your code. The latter style, while describing the correct behavior, may confuse some synthesizers that don't expect to see clocks that are both sensitive to positive and negative edge.
The two blocks are VERY different.
The top one gives you a flip-flop while the bottom one gives you a latch with a multiplexer with the CLK as the select signal.
The critical difference between the two blocks is that the top one is a synchronous block i.e. the posedge clk part while the bottom one is asynchronous with the CLK level, not edge.
A verilog simulator could do left-hand sampling of CLK, effectively making the the case(CLK) version the same as a negedge CLK flop. Otherwise the simulator will treat it like a posedge CLK flop. It really depends how it is handled in the scheduler of specific simulator (or how a particular synthesizer will process it).
The most common codding styles all use the first condition. It is explicitly clear to the synthesizer and anyone reading the code that state is intended to be a flip-flop with a positive edge clocking trigger.
There is also a simulation performance differences. The posedge CLK performances 2 CPU operations every clock period, while the case(CLK) will perform 6 CPU operations every clock period. Granted in this example the differences is insignificance, but in large designs the poor coding used everywhere will add up to hours of simulation time wasted.
Wondering about the behavior of event control statements in an always block:
always #(posedge clk) begin: TEST
...
#(wait_for_signal_from_subsystem);
...
#(wait_for_another_signal_from_subsystem);
...
end
Will the process be "stuck" until the event signals come in, or will it restart every time a clk edge comes in ?
Also is this synthesizable (Quartus II says yes, but not simulated yet...) ? and is this a good practice or is there an alternative better approach to this problem ?
Yes, it is 'stuck' as you would say. Only one 'loop' of the block can be active at a time, it will not reenter if it has not completed the loop.
The thing you are trying to do there is likely not synthesizable, due to the wait operations inside the block.
I don't know the exact specifics of your design, but I would approach this with a small finite state machine. I assume that the signals from your subsystem are not faster than the clock, so it would look something like:
always #* begin
if(state_f == `WAIT_FOR_FIRST)
state_nxt = got_first_signal ? `WAIT_FOR_SECOND : `WAIT_FOR_FIRST;
else if(state_f == `WAIT_FOR_SECOND)
state_nxt = got_second_signal ? `DONE_STATE : `WAIT_FOR_SECOND;
else if(state_f == `DONE_STATE)
state_nxt = `WAIT_FOR_FIRST;
else
state_nxt = 2'bxx;
end
always #(posedge clk) begin
state_f <= state_nxt;
end
Assuming you are designing hardware and not non-synthesized testbench code, this not a good practice and likely won't do what you want anyways.
From a language perspective, this will compile and simulate. It will block waiting on the events within the always blocks and NOT restart on each posedge of the clock. I could not find a spec reference for this but it's what I observed in simulation. I'm curious what this would synthesize to if you even get it to synthesize with no errors.
If the signal from the other subsystem is already in the same clock domain (synchronous to clk), then you can just check the state of it on each clock edge, and use this do something.
always #(posedge clk) begin: TEST
if (the_other_signal == 1'b1) begin
...
end
end
Some other things to consider:
Maybe you only care about when the signal assert/deasserts. In that case you need to do an edge detection.
If the signal is asynchronous to clk, then you have a clock domain crossing and you need to synchronize the incoming signal before you look at it.