I need to create a circuit based on the Boolean function: Y = AB’ + B’C’ + A’BC using only an 8 to 1 multiplexer. Then recreate the circuit using only a 4 to 1 multiplexer and NOT gates.
I figured the truth table to be:
A B C | Y
0 0 0 | 1
0 0 1 | 0
0 1 0 | 0
0 1 1 | 1
1 0 0 | 1
1 0 1 | 1
1 1 0 | 0
1 1 1 | 0
But I don't understand how to make the circuit using only a 8 to 1 multiplexer.
Well,
1- Take an 8 to 1 multiplexer
2- Connect A, B y C to the three input
3- connect Y0, Y3, Y4 and Y5 to Vcc, and the rest to ground.
This logical function is made with just one 3x1 multiplexer and no other component.
To make it with 4x1, yo need to connect, for example A and B to the two control inputs, and the 4 input Y0, Y1, Y2, Y3 to the Vcc, ground, C or not(C) as needed, but yo need at least one not gate.
It seem as there is not a solution without a not gate, because por A=B=C=0->Y=1, and A=B=C=1->Y=0
Related
I am trying to understand the the MCTAL output of a spherical TMESH tally. What I want is to create one tally bin that has the following boundaries 1.9 cm and 2.1 cm in the radial direction, 88 to 92 degrees in theta and 180 to 360 degrees in the phi direction. my input for the tally is
C tally card spherical mesh energy tally
TMESH
SMESH1:p DOSE 1 1 1 1.0 PEDEP MFACT 1 1 0 1.0
CORA1 1.9 2.1
CORB1 88 92
CORC1 180 360
Now what I expect is one result for that volume what I get are eight values as shown below.
ntal 1
1
tally 1 -1 -3
0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
f 4 0 1 2 2
1.90000E+00 2.10000E+00
0.00000E+00 8.80000E+01 9.20000E+01
0.00000E+00 1.80000E+02 3.60000E+02
d 1
u 1
s 2
m 1
c 1
e 1
t 1
vals
5.57481E-04 0.0067 7.68088E-09 0.0493 8.24471E-03 0.0046 1.38395E-07 0.0639
5.53931E-04 0.0046 7.44313E-09 0.0287 8.24244E-03 0.0042 1.27868E-07 0.0553
I am assuming that these eight vals correspond to the eight points that that are listed under f. Does TMESH only give one values for individual points on a grid or can it be used to create a volume within which to obtain a result? lastly to what points do what vals correspond to ?
The matrix bellow the vals is true value of your meshtally result.
but
you must load data to Matlab and reshape it to your mesh tally matrix
With your SMESH setup you score both dose and energy deposition. This causes two bins along the segment axis (the "s 2" record in your mctal). Then, you have only 1 bin along the radial direction (1.9-2.1 cm) and actually TWO bins along each of the angular directions (0-88, 88-92, and 0-180, 180-360) which sums up to 2^3 = 8 bins. The mctal file format is described in the manual: it'a 11-dimension loop. In your case only the s, j and k axes are divided, so it's actully a 3D loop (in this exact order: s being the outer, k - the inner loop). Therefore the value for your volume is either the 4th (1.38395E-07 0.0639) or last (1.27868E-07 0.0553) record depending on whether you need dose or energy deposition.
Here is a simple replace for a rank-1 list using the I. verb:
y=: _3 _2 _1 1 2 3
0 (I. y<0) } y
The result is
0 0 0 1 2 3
How do I do such a replacement for a rank-2 matrix?
For example,
y2 =: 2 3 $ _3 _2 _1 1 2 3
0 (I. y2<0) } y2
I got (J806)
|index error
| 0 (I.y2<2)}y2
The reason seems to be
(I. y2 < 0)
gives
0 1 2
0 0 0
which isn't taken well by }.
The simplest answer for this problem is to use dyadic >. (Larger of) ...
0 >. y2
0 0 0
1 2 3
If you want to use a more general conditional replacement criteria, then the following form may be useful:
(0 > y2)} y2 ,: 0
0 0 0
1 2 3
If you want it as a verb then you can use the gerund form (v1`v2)} y ↔ (v1 y)} (v2 y) :
(0 > ])`(0 ,:~ ])} y2
0 0 0
1 2 3
If your question is more about scatter index replacement then that is possible too. You need to get the 2D indices of positions you want to replace, for example:
4 $. $. 0 > y2
0 0
0 1
0 2
Now box those indices and use dyadic }:
0 (<"1 (4 $. $. 0 > y2)) } y2
0 0 0
1 2 3
Again you can turn this into a verb using a gerund left argument to dyadic } (x (v0`v1`v2)} y ↔ (x v0 y) (x v1 y)} (x v2 y)) like this:
0 [`([: (<"1) 4 $. [: $. 0 > ])`]} y2
0 0 0
1 2 3
Or
100 101 102 [`([: (<"1) 4 $. [: $. 0 > ])`]} y2
100 101 102
1 2 3
To tidy this up a bit you could define getIdx as separate verb...
getIdx=: 4 $. $.
0 [`([: <"1#getIdx 0 > ])`]} y2
0 0 0
1 2 3
This is not a good solution. My original approach was to change the rank of the test so that it looks at each row separately, but that does not work in the general case (see comments below).
[y2 =: 2 3 $ _3 _2 _1 1 2 3
_3 _2 _1
1 2 3
I. y2<0
0 1 2
0 0 0
0 (I. y2<0)"1 } y2 NB. Rank of 1 applies to each row of y2
0 0 0
1 2 3
According to the image below, it says the output ports are from F0-F7H. My question is how are these ports addresses determine? For example, F0(active low) (Y0) is determine from the inputs A0-A7 inputs? If so, how are these input ports mathematically come to F0?
The 74ALS138 is a 1-8 demultiplexer, this means it takes a number between 0 and 7 and activates one of its eight output lines (active low).
The A, B and C input signals are the three bit encoding the input number (23 = 8) while G1, GA and GB are the enable signals.
To enable the chip G1 must be high and GA and GB must be low, any other combination will disable the chip (all output is high).
To have G1 high we must have the bit 4 of the address high, analogously bit 5, 6 and 7 must be high.
Finally, bit 3 must be low.
This gives an address of the form 1111 0xxx, ranging from 0f0h to 0f7h.
The lowest three bits select the output line.
Regarding the tie between A, B and C and the outputs, you can start with a truth table:
A B C Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
0 0 0 0 1 1 1 1 1 1 1
0 0 1 1 0 1 1 1 1 1 1
0 1 0 1 1 0 1 1 1 1 1
0 1 1 1 1 1 0 1 1 1 1
1 0 0 1 1 1 1 0 1 1 1
1 0 1 1 1 1 1 1 0 1 1
1 1 0 1 1 1 1 1 1 0 1
1 1 1 1 1 1 1 1 1 1 0
Each output Yi must be computed independently; since each of them is zero exactly once, there is no need to optimize it with a Karnaugh map and since there are a lot of ones, working with Maxterms is definitively better.
So for example for Y0 the formula is
Y0 = A + B + C
Due to the rules when dealing with maxterms (It's a product of sum, each factor being negated iif the input variable is 1).
The other relations are
Y1 = A + B + C'
Y2 = A + B' + C
Y3 = A + B' + C'
Y4 = A' + B + C
Y5 = A' + B + C'
Y6 = A' + B' + C
Y7 = A' + B' + C'
This doesn't take into account the enable inputs, internally we can have a single enable signal E by taking E = G1 * GA' * GB' then the truth table for Y0 becomes
E A B C Y0
0 0 0 0 1
0 0 0 1 1
0 0 1 0 1
0 0 1 1 1
0 1 0 0 1
0 1 0 1 1
0 1 1 0 1
0 1 1 1 1
1 0 0 0 0
1 0 0 1 1
1 0 1 0 1
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1
This just translates to Y0 = E' + A + B + C.
If you consider that X + Y === (X' * Y')' by De Morgan's laws and call (X * Y)' NAND you see that Y0 = NAND(E, A', B', C') which is exactly the implementation in the 74ALS138 datasheet:
Datasheet courtesy of Matt Clark
The table in the data sheet seems quite clear: Y0 is active if A0, A1, A2, and A3 are low and A4, A5, A6, and A7 are high. Y1 is active under all the same conditions except A0 is high.
Thanks for the comments to help me connect the dots in figuring out how the address is map to the input address
I want to design a gate-level combinational circuit that implements the below logic. Is it possible to do it without using Adder?
...
input wire [3:0] in,
input wire sel,
output wire [3:0] out
...
assign out = ({4{sel}} & (~in + 1)) | ({4{~sel}} & in);
The above verilog code will be realized into - 4 inverters, 1 full adder and 1 multiplexer. Is it possible to optimize it further?
The idea is to incorporate sel in 2's complement logic and produce a gate circuit that consumes lesser number of gates than adder circuit. Is it really possible?
Try using the Karnaugh map and solve for just the (~in + 1) term. If you set up the K-map and solve for one bit of the result at a time
// Input Result
// A B C D --> ~{A B C D} --> ~{A B C D}+1
// 0 0 0 0 1 1 1 1 0 0 0 0
// 0 0 0 1 1 1 1 0 1 1 1 1
// 0 0 1 0 1 1 0 1 1 1 1 0
// 0 0 1 1 1 1 0 0 1 1 0 1
// 0 1 0 0 1 0 1 1 1 1 0 0
// 0 1 0 1 1 0 1 0 1 0 1 1
... I'll let you write the rest of the map... but a few things start to pop out.
The Result bit D, is always the same as the Input D
The Result bit C appears to be a Input C XOR Input D
If you do some more K map, you will probably find a logical expression for Result bits A and B
How to Design a Mealy sequential network which investigates an input sequence X
and produces an output Z which is determined by two rules. The initial output
from the network is Z=0. Thereafter, the output Z will equal the preceding
value of X (rule 1) until the input sequence 010 occurs. Starting with the next
input after 010, the output Z will equal the complement of the present value
of X (rule 2) until the sequence 101 occurs. Starting with the next input after
101, the network output is again determined by rule 1, etc. Note that
overlapping 010 and 101 sequences may occur. Example:
Rule: 1 1 1 1 1 1 2 2 2 2 2 1 2
a.i.1.a.i. X= 0 1 1 0 1 0 0 1 1 0 1 0 1
a.i.1.a.ii. Z= 0 0 1 1 0 1 1 0 0 1 0 1 0
umm, draw a state diagram and start coding?