I find that I end up in this situation on Ubuntu often, and I was wondering if there's a neat way to solve it.
Suppose I am writing some C++ programs, say a.cpp, b.cpp and c.cpp. During testing, I generate a lot related files like a.out, .a.out~, .a.un~ etc. If at some point later I realise that I no longer need a.cpp, I can perform rm a.cpp. But then I am left with a clutter of associated junk that is no longer relevant.
I am aware that I can perform periodic rm .*.un~ but I'm hoping for a better way. Is there a way I can get rm to prompt me at the point of deleting a.cpp with something like
rm: remove regular file 'a.cpp'? y
rm: remove associated file '.a.un~' too?
which I can then say 'y' or 'n' to?
This is an example Makefile.
all:
g++ -o a a.cpp
clean:
rm -f *~
Make sure to keep the tabulators in front of g++ and rm.
Compile with make all and clean up with make clean.
Is there a simple way in SCons to create a target which is considered up-to-date if the named file is verified not to exist? (And of course, to have a builder which deletes the file if it does exist...)
For instance:
b_file = env.Command("files", ["file1", "file2", "file3"],
"build-files -o $TARGET $SOURCES")
env.Depends(b_file,env.FileMustNotExist("file4"))
The idea would be that before building "files", SCons would make sure not only that "file1", "file2", and "file3" are present, but that "file4" does not exist.
I know that for this particular case I could approximate what I want by adding "rm -f file4; " to the beginning of the command, but that's not exactly the same. In particular, if I add the "rm" command to the builder, and then create "file4" outside of SCons, re-running SCons won't delete "file4" unless one of the other sources has changed.
I'd want something such that creating "file4" and re-running SCons would result in simply deleting "file4" and indicating that "files" is now built.
To my knowledge this is not foreseen in the design, and therefore not possible. Note how SCons is a file-oriented build system, so its main task is to create files...and not deleting them.
In newer versions there is the Pseudo target, which is intended for build actions that don't create an actual output file...but it's not able to delete files, if I remember correctly.
So, it looks as if the "rm -f file" strategy is still the best way to go. You might want to use Python's os.path.isfile and os.unlink though, to stay compatible over the different platforms.
I try to achieve something that I imagined very simple, but which is finally harder than expected.
I have a folder : source/. I have a second one : target/. I create a file test.jar in my first folder. Then, I want this file to appear and be executable in my second folder. I see 3 options :
manually copy/paste my file. It works but... I don't want to do it each time I update my file.
symbolic link. It works, but if I execute the jar file, the context is source/ and not target/ like I would like.
hard link. That's exactly what I need, but the issue is that test.jar is not modified, but generated. This means that after erasing source/test.jar, target.test.jar still references the old file... Is it possible to force the 2 files to have always the same value ?
Thanks for your help !
EDIT : For now, I solved the problem by adding a line to copy my file from source/ to target/ inside a script that I will execute anyway after generating the jar. I think that what I wanted to do is actually impossible. It would need a new kind of linking which links the content of 2 files given their pathname and not their inode...
Don't create a soft link of the file. Create a soft link of the entire folder.
Something like
ln -s {whatever path}/source/ {whatever path}/target
Then the folder target/ is a folder-link to the first folder and context should be the same.
You can also try using git (locally) and checkout source/ to folder target.
You can try creating an executable shell script named test.jar in the target directory and make it call the path/source/test.jar passing forwarding all the parameters. Something like:
#!/bin/bash
path/source/test.jar "$#"
I am trying to get a .tar.gz file name from a new generated folder (one step above).
I tried to use wildcard , but with no luck,
In my makefile, I tried:
...
...
...
other parts
...
deb:
python setup.py sdist --- this step will generate a new folder called dist
cd dist; ls -l --- from here, I see the file is shown.
echo $(wildcard dist/*.tar.gz) (also tried dist/pylink*.tar.gz, dist/*.gz) --fails!
I run it with make -f makefile deb.
I always got nothing from wildcard
But if I leave the folder generated by python, and rerun the file above, I can see the file name is written to the console. Anyone knows why? How should I do to get the file name? I need to use the filename and extend the filename to another one.
many many thanks!
You don't say so explicitly but I assume that, because you're using $(wildcard ...), the lines you provide are part of a GNU make makefile rule. It's best to provide a working example, when asking for help, not just a small bit of one.
The problem you're having is that make expands ALL variables and functions in ALL lines of the recipe, before it starts the first line of the recipe. So even though the $(wildcard ...) doesn't appear until the third line of the recipe, it's expanded before the first line is run. When the $(wildcard ...) function runs, those files don't yet exist so it expands to nothing.
Why don't you just use the shell globbing, since you're in a shell anyway?
python setup.py sdist
cd dist; ls -l
echo dist/*.tar.gz
I have a makefile that builds and then calls another makefile. Since this makefile calls more makefiles that does the work it doesn't really change. Thus it keeps thinking the project is built and up to date.
dnetdev11 ~ # make
make: `release' is up to date.
How do I force the makefile to rebuild the target?
clean = $(MAKE) -f ~/xxx/xxx_compile.workspace.mak clean
build = svn up ~/xxx \
$(clean) \
~/cbp2mak/cbp2mak -C ~/xxx ~/xxx/xxx_compile.workspace \
$(MAKE) -f ~/xxx/xxx_compile.workspace.mak $(1) \
release:
$(build )
debug:
$(build DEBUG=1)
clean:
$(clean)
install:
cp ~/xxx/source/xxx_utility/release/xxx_util /usr/local/bin
cp ~/xxx/source/xxx_utility/release/xxxcore.so /usr/local/lib
Note: Names removed to protect the innocent
Final Fixed version:
clean = $(MAKE) -f xxx_compile.workspace.mak clean;
build = svn up; \
$(clean) \
./cbp2mak/cbp2mak -C . xxx_compile.workspace; \
$(MAKE) -f xxx_compile.workspace.mak $(1); \
.PHONY: release debug clean install
release:
$(call build,)
debug:
$(call build,DEBUG=1)
clean:
$(clean)
install:
cp ./source/xxx_utillity/release/xxx_util /usr/bin
cp ./dlls/Release/xxxcore.so /usr/lib
The -B switch to make, whose long form is --always-make, tells make to disregard timestamps and make the specified targets. This may defeat the purpose of using make, but it may be what you need.
You could declare one or more of your targets to be phony.
A phony target is one that is not really the name of a file; rather it
is just a name for a recipe to be executed when you make an explicit
request. There are two reasons to use a phony target: to avoid a
conflict with a file of the same name, and to improve performance.
...
A phony target should not be a prerequisite of a real target file; if
it is, its recipe will be run every time make goes to update that
file. As long as a phony target is never a prerequisite of a real
target, the phony target recipe will be executed only when the phony
target is a specified goal
One trick that used to be documented in a Sun manual for make is to use a (non-existent) target '.FORCE'. You could do this by creating a file, force.mk, that contains:
.FORCE:
$(FORCE_DEPS): .FORCE
Then, assuming your existing makefile is called makefile, you could run:
make FORCE_DEPS=release -f force.mk -f makefile release
Since .FORCE does not exist, anything that depends on it will be out of date and rebuilt.
All this will work with any version of make; on Linux, you have GNU Make and can therefore use the .PHONY target as discussed.
It is also worth considering why make considers release to be up to date. This could be because you have a touch release command in amongst the commands executed; it could be because there is a file or directory called 'release' that exists and has no dependencies and so is up to date. Then there's the actual reason...
Someone else suggested .PHONY which is definitely correct. .PHONY should be used for any rule for which a date comparison between the input and the output is invalid. Since you don't have any targets of the form output: input you should use .PHONY for ALL of them!
All that said, you probably should define some variables at the top of your makefile for the various filenames, and define real make rules that have both input and output sections so you can use the benefits of make, namely that you'll only actually compile things that are necessary to copmile!
Edit: added example. Untested, but this is how you do .PHONY
.PHONY: clean
clean:
$(clean)
make clean deletes all the already compiled object files.
If I recall correctly, 'make' uses timestamps (file modification time) to determine whether or not a target is up to date. A common way to force a re-build is to update that timestamp, using the 'touch' command. You could try invoking 'touch' in your makefile to update the timestamp of one of the targets (perhaps one of those sub-makefiles), which might force Make to execute that command.
This simple technique will allow the makefile to function normally when forcing is not desired. Create a new target called force at the end of your makefile. The force target will touch a file that your default target depends on. In the example below, I have added touch myprogram.cpp. I also added a recursive call to make. This will cause the default target to get made every time you type make force.
yourProgram: yourProgram.cpp
g++ -o yourProgram yourProgram.cpp
force:
touch yourProgram.cpp
make
I tried this and it worked for me
add these lines to Makefile
clean:
rm *.o output
new: clean
$(MAKE) #use variable $(MAKE) instead of make to get recursive make calls
save and now call
make new
and it will recompile everything again
What happened?
1) 'new' calls clean.
'clean' do 'rm' which removes all object files that have the extension of '.o'.
2) 'new' calls 'make'.
'make' see that there is no '.o' files, so it creates all the '.o' again. then the linker links all of the .o file int one executable output
Good luck
As abernier pointed out, there is a recommended solution in the GNU make manual, which uses a 'fake' target to force rebuilding of a target:
clean: FORCE
rm $(objects)
FORCE: ;
This will run clean, regardless of any other dependencies.
I added the semicolon to the solution from the manual, otherwise an empty line is required.
As per Miller's Recursive Make Considered Harmful you should avoid calling $(MAKE)! In the case you show, it's harmless, because this isn't really a makefile, just a wrapper script, that might just as well have been written in Shell. But you say you continue like that at deeper recursion levels, so you've probably encountered the problems shown in that eye-opening essay.
Of course with GNU make it's cumbersome to avoid. And even though they are aware of this problem, it's their documented way of doing things.
OTOH, makepp was created as a solution for this problem. You can write your makefiles on a per directory level, yet they all get drawn together into a full view of your project.
But legacy makefiles are written recursively. So there's a workaround where $(MAKE) does nothing but channel the subrequests back to the main makepp process. Only if you do redundant or, worse, contradictory things between your submakes, you must request --traditional-recursive-make (which of course breaks this advantage of makepp). I don't know your other makefiles, but if they're cleanly written, with makepp necessary rebuilds should happen automatically, without the need for any hacks suggested here by others.
If you don't need to preserve any of the outputs you already successfully compiled
nmake /A
rebuilds all
It was already mentioned, but thought I could add to using touch
If you touch all the source files to be compiled, the touch command changes the timestamps of a file to the system time the touch command was executed.
The source file timstamp is what make uses to "know" a file has changed, and needs to be re-compiled
For example: If the project was a c++ project, then do touch *.cpp, then run make again, and make should recompile the entire project.
It actually depends on what the target is. If it is a phony target (i.e. the target is NOT related to a file) you should declare it as .PHONY.
If however the target is not a phony target but you just want to rebuild it for some reason (an example is when you use the __TIME__ preprocessing macro), you should use the FORCE scheme described in answers here.
http://www.gnu.org/software/make/manual/html_node/Force-Targets.html#Force-Targets
On my Linux system (Centos 6.2), there is a significant difference between declaring the target .PHONY and creating a fake dependency on FORCE, when the rule actually does create a file matching the target. When the file must be regenerated every time, it required both
the fake dependency FORCE on the file, and .PHONY for the fake dependency.
wrong:
date > $#
right:
FORCE
date > $#
FORCE:
.PHONY: FORCE