Verilog Always statement for 4 Demux - verilog

Question

This is my Verilog code for the procedural modeling of the 4 Demux:
//4 Bit demux in Gate level
module HW3_PM(input [3:0] I, input Sel, output [3:0] A, output [3:0] B);
always#(*)
begin
case(Sel)
1'b0: begin
A = ~Sel&I;
end
1'b1: begin
B = Sel&I;
end
default: begin
end
endcase
end
endmodule
And I input to receive this error:
eos$ ncverilog +access+r HW3_PM.v HW2_Demux4_tb.v +gui
ncverilog: 09.20-s019: (c) Copyright 1995-2010 Cadence Design Systems, Inc.
file: HW3_PM.v
A = ~Sel&I;
|
ncvlog: *E,WANOTL (HW3_PM.v,8|6): A net is not a legal lvalue in this context [9.3.1(IEEE)].
B = Sel&I;
|
ncvlog: *E,WANOTL (HW3_PM.v,11|6): A net is not a legal lvalue in this context [9.3.1(IEEE)].
module worklib.HW3_PM:v
errors: 2, warnings: 0
file: HW2_Demux4_tb.v
ncverilog: *E,VLGERR: An error occurred during parsing.
Review the log file for errors with the code *E and fix
those identified problems to proceed. Exiting with code (status 1).
I've tried changing and adding A and B as both reg and wire but it causes higher errors. I tried changing to posedge of the clock and get a different error. Your help is appreciated.
NEW:
Changed code:
//4 Bit demux in Gate level
module HW3_PM(input [3:0] I, input Sel, output [3:0] A, output [3:0] B);
reg A, B;
always#(*)
begin
case(Sel)
1'b0: begin
A = ~Sel&I;
end
1'b1: begin
B = Sel&I;
end
default: begin
end
endcase
end
endmodule
Received error:
file: HW3_PM.v
module HW3_PM(input [3:0] I, input Sel, output [3:0] A, output [3:0] B);
|
ncvlog: *E,BADIOO (HW3_PM.v,2|53): input/output/inout 'A' declared as vector, then redeclared as scalar [3.3(IEEE)].
reg A, B;
|
ncvlog: *W,ILLPDX (HW3_PM.v,4|5): Multiple declarations for a port not allowed in module with ANSI list of port declarations (port 'A') [12.3.4(IEEE-2001)].
module HW3_PM(input [3:0] I, input Sel, output [3:0] A, output [3:0] B);
|
ncvlog: *E,BADIOO (HW3_PM.v,2|69): input/output/inout 'B' declared as vector, then redeclared as scalar [3.3(IEEE)].
reg A, B;
|
ncvlog: *W,ILLPDX (HW3_PM.v,4|8): Multiple declarations for a port not allowed in module with ANSI list of port declarations (port 'B') [12.3.4(IEEE-2001)].
module worklib.HW3_PM:v
errors: 2, warnings: 2
file: HW2_Demux4_tb.v
ncverilog: *E,VLGERR: An error occurred during parsing.
Review the log file for errors with the code *E and fix
those identified problems to proceed. Exiting with code (status 1)

Answer 1

module HW3_PM(
input [3:0] I,
input Sel,
output reg [3:0] A,
output reg [3:0] B
);
always#(*)
begin
if(~Sel) begin
A = I;
B = 0;
end else begin
A = 0;
B = I;
end
end
endmodule
or
module HW3_PM(
input [3:0] I,
input Sel,
output wire [3:0] A,
output wire [3:0] B
);
assign A = ~sel&I;
assign B = sel&I;
endmodule
or
module HW3_PM(
input [3:0] I,
input Sel,
output reg [3:0] A,
output reg [3:0] B
);
always#(*)
begin
case(Sel)
0: begin
A = I;
B = 0;
end
1: begin
A = 0;
B = I;
end
endcase
end
endmodule
or
module HW3_PM(input [3:0] I,input Sel,output wire [3:0] A, output wire [3:0] B);
and selA[3:0] (A, ~sel, I);
and selB[3:0] (B, sel, I);
endmodule