In my book as an example it has:
wire [n-1:0] c = {1'b1,(~r[n-1:1] & c[n-1:1])};
If n=4 then c is 4 bits but the concatenation however makes 5 bits! 0.o
)r is there something I don't understand about Verilog here, that maybe the case.
The concatenation is infact just 4 bits. r[n-1:1] is an n-1 bit value which in this case is 3. Note that r[n-1:1] means the bits starting from 2nd bit (index = 1) to nth bit ( index = n-1). So a 3 bit value concatenated with 1b'1 gives a 4 bit value.
Related
Hello I am new to the programming world. I have a project for my ece 171 class that I have been trying to figure out on my own but cannot. I had a project before where I needed to design a 2 bit comparator which I did design successfully. Now I am supposed to take that 2 bit comparator and alter it as well as write some more verilog code that will compare 8 bits with each other using my expanded 2 bit program. My problem is that I don't know where to even start. My professor said always start with a black box and then truth table. My initial instinct is to create a 16 bit truth table which I know is wrong. But I don't even know where to start? Any suggestions? I feel like if I could just be shown where the path starts that it would start coming to me.
My 2-bit comparator code below.
//two 2-bit input Values Comparer Behavioral Dataflow
//Defining Module and Parameters
module BcompareA(A, B, GT, EQU, LT);
input [1:0] A;
input [1:0] B;
output GT;//when a is greater than b
output EQU;//when a is equal to b
output LT;//when a is less than b
//Boolean Output Descriptions
assign GT = A[1]&~B[1]
| A[1]&A[0]&~B[0]
| A[0]&~B[1]&~B[0]
assign EQU = ~A[1]&~A[0]&~B[1]&~B[0]
| ~A[1]&A[0]&~B[1]&B[0]
| A[1]&A[0]&B[1]&B[0]
| A[1]&~A[0]&B[1]&~B[0]
assign LT = ~A[1]&B[1]
| ~A[1]&~A[0]&B[0]
| ~A[0]&B[1]&B[0]
endmodule
You should use yours 2 bit comparator to compare pairs of bits [7:6], [5,4],...
Lets start with EQU output - it is the easiest. A and B would be equal if all its pairs would be equal. So logic is simple.
Make a notice that A would be greater if its highest bits are greater (GT_76 == 1 ) or highest bits are equal( EQU_76 == 1 ) and next pair would be greater ( GT_54 = 1 ) or etc.
Finally A would be less if it is not greater and not equal.
I'm trying to design a system that takes an 8 byte data input and an 8 bit valid input every clock cycle where each bit on the valid input either validates or invalidates a data byte.
input wire [63:0] d_in;
input wire [7:0] v_in;
The program should process d_in aligning all the valid bytes as follows.
(where B is a valid byte and X is an invalid byte)
Instance 1:
d_in = B1 B2 X X B3 X B4 B5
d_out = B1 B2 B3 B4 B5 X X X
Instance 2:
d_in = X B1 B2 B3 X B4 B5 B6
d_out = B1 B2 B3 B4 B5 B6 X X
I've mainly worked with algorithms before where all bit manipulation was the same every iteration e.g.assign d_out [7:0] = d_in [15:8]; but the fact that the quantity and order of valid bytes can change with every data input means this strategy cannot be used.
My question:
Is there a way to realise this function in using Verilog or VHDL? If so can someone point me towards a high level solution or some relevant reading so I can understand this concept better. I think if I understood at a high level then I'd be able to take a stab a coding it but currently I'm not even sure what I need to be coding.
Thanks
Zach
Since you asked for high level I will give a pseudocode example of something that might work, or at least get you going.
d_out = '0; //Assuming that the X bytes can be set to zero in the output.
bytes = 0;
for i in range(8)
if v_in[i]
d_out[bytes*8 +: 8] = d_in[i*8 +: 8] //Note the +: notation which is not pseudo, but verilog.
bytes++
Now perform this sequential code in an always block and you should be set.
Note: How the synthesized result from this will look is not entierly clear to me, but i suspect it will generate quite a bit of hardware.
I have something similar but not quite.
Input data into a FIFO, pre-calculate a byte-enable with the FIFO entries.
On the output side, read the the byte enable portions and use it to shift out bytes. So there are only eight conditions to satisfy for the byte enable...
1 byte, byteEn(0 downto 1) = "10", shift left 1 byte
2 bytes, byteEn(0 downto 2) = "110", shift left 2 bytes
3 bytes, byteEn(0 downto 3) = "1110", shift left 3 bytes
...and so on...
As you shift, read in the next word using the FIFOs read enable.
Note you will need to take care of when the FIFO is empty but not halt the pipeline so data already present continues to be shifted out.
Not sure how complicated it will be as I have glossed over it a bit.
I'm trying to implement COS X function in Verilog using Taylor series. The problem statement presented to me is as below
"Write a Verilog code to compute cosX using Taylor series approximation. Please attach the source and test bench code of the 8-bit outputs in signed decimal radix format for X = 0° to 360° at the increment of 10° "
I need to understand a couple of things before i proceed. Please correct me if i am wrong someplace
Resolution calculation : 10° increments to cover 0° to 360° => 36 positions
36 in decimal can be represented by 6 bits. Since we can use 6 bits, the resolution is slightly better by using 64 words. The 64 words represent 0° to 360° hence each word represents a resolution of 5.625° ie all values of Cos from 0° to 360° in increments of 5.625°. Thus resolution is 5.625°
Taylor series calculation
Taylor series for cos is given by Cos x approximation by Taylor series
COS X = 1 − (X^2/2!) + (X^4/4!) − (X^6/6!) ..... (using only 3~4 terms)
I have a couple of queries
1) While it is easy to generate X*X (X square) or X cube terms using a multiplier, i am not sure how to deal with the extra bits generated during calculation of X square or X cube terms . Output is 8 bits only
eg X=6 bits ; X square =12 bits ; X cube = 18 bits.
Do i generate them anyways and later ignore them by considering just the MSB 8 bits of the entire result ? ... such a cos wave would suck right ?
2) I am not sure how to handle the +1 addition at start of Taylor series ...COS X = 1 − (X^2/2!) + (X^4/4!) .... Do i add binary 1 directly or do i have to scale the 1 as 2^8 = 255 or 2^6 = 64 since i am using 6 bits at input and 8 bits at output ?
I think this number series normally gives a number in the range +1 to -1. SO you have to decide how you are going to use your 8 bits.
I think a signed number with 1 integer bit and 7 fractional bits, you will not be able to represent 1, but very close.
I have a previous answer explaining how to use fixed-point with verilog. Once your comfortable with that you need to look at how bit growth occurs during multiply.
Just because you are outputting 1 bit int, 7 bit frac internally you could (should) use more to compute the answer.
With 7 fractional bits a 1 integer would look like 9'b0_1_0000000 or 1*2**7.
Was trying to solve this popular interview question - http://www.careercup.com/question?id=3406682
There are 2 approaches to this that i was able to grasp -
Brian Kernighan's algo -
Bits counting algorithm (Brian Kernighan) in an integer time complexity
Lookup table.
I assume when people say use a lookup table, they mean a Hashmap with the Integer as key, and the count of number of set bits as value.
How does one construct this lookup table? Do we use Brian's algo to to count the number of bits the first time we encounter an integer, put it in hashtable, and next time we encounter that integer, retrieve value from hashtable?
PS: I am aware of the hardware and software api's available to perform popcount (Integer.bitCount()), but in context of this interview question, we are not allowed to use those methods.
I was looking for Answer everywhere but could not get the satisfactory explanation.
Let's start by understanding the concept of left shifting. When we shift a number left we multiply the number by 2 and shifting right will divide it by 2.
For example, if we want to generate number 20(binary 10100) from number 10(01010) then we have to shift number 10 to the left by one. we can see number of set bit in 10 and 20 is same except for the fact that bits in 20 is shifted one position to the left in comparison to number 10. so from here we can conclude that number of set bits in the number n is same as that of number of set bit in n/2(if n is even).
In case of odd numbers, like 21(10101) all bits will be same as number 20 except for the last bit, which will be set to 1 in case of 21 resulting in extra one set bit for odd number.
let's generalize this formual
number of set bits in n is number of set bits in n/2 if n is even
number of set bits in n is number of set bit in n/2 + 1 if n is odd (as in case of odd number last bit is set.
More generic Formula would be:
BitsSetTable256[i] = (i & 1) + BitsSetTable256[i / 2];
where BitsetTable256 is table we are building for bit count. For base case we can set BitsetTable256[0] = 0; rest of the table can be computed using above formula in bottom up approach.
Integers can directly be used to index arrays;
e.g. so you have just a simple array of unsigned 8bit integers containing the set-bit-count for 0x0001, 0x0002, 0x0003... and do a look up by array[number_to_test].
You don't need to implement a hash function to map an 16 bit integer to something that you can order so you can have a look up function!
To answer your question about how to compute this table:
int table[256]; /* For 8 bit lookup */
for (int i=0; i<256; i++) {
table[i] = table[i/2] + (i&1);
}
Lookup this table on every byte of the given integer and sum the values obtained.
I am doing a divider circuit in verilog and using the non-restoring division algorithm.
I am having trouble representing the remainder as a fractional binary number.
For example if I do 0111/0011 (7/3) I get the quotient as 0010 and remainder as 0001 which is correct but I want to represent it as 0010.0101.
Can Someone help ??
Suppose, as in your example, you are dividing 4 bit numbers, but want an extra 4 bits of fractional precision in the result.
One approach is to simply multiply the numerator by 2^4 before doing the division.
i.e.
instead of
0111/0011 = 0010 (+remainder)
do
01110000/0011 = 00100101 (+remainder)
hi just do mathematics !!!
you have already got the Q(quotient) and R(remainder) , now with the remainder you multiply that with 10(decimal) in binary 1010 that for example
7/3 gives 2 as Q and 1 as remainder than just multiply this 1 with 10 then again apply your logic which gives 10/3 gives 3 as Q so your answer will be
3(Q(first_division)).3(second division-Q)
try it it is working . and very easy to implement in verilog .