It's verilog code and can't simulate because of syntax error. Anyone know how to solve it?
assign x = (Status == 2'b00)?
{Board[0],1'b0,1'b0,Board[2],1'b0,1'b0,Board[1],1'b0,Board[3],1'b0,1'b0,Board[5],1'b0,1'b0,Board[4],1'b0,1'b0,Board[6],1'b0,1'b0,Board[8],1'b0,1'b0,Board[7],1'b0,Board[9],1'b0,1'b0,Board[11],1'b0,1'b0,Board[10],1'b0,Board[12],1'b0,1'b0,Board[14],1'b0,1'b0,Board[13],1'b0,Board[15],1'b0,1'b0,Board[17],1'b0,1'b0,Board[16],1'b0}:
(Status == 2'b01)?
64'b0110000001100000011000000110000000000000000000000000000000000000:
(Status == 2'b10)?
64'b1101101011011010110110101101101000000000000000000000000000000000:
(Status == 2'b11)?
64'b1001110011101111011100100100000100000000000000000000000000000000:
Form minimum code change:
//(Status == 2'b11)?// <- comment out for final condition
64'b1001110011101111011100100100000100000000000000000000000000000000 ; // <- semicolon, not colon
Better yet convert to a case statement. Easier to read and debug.
reg [63:0] x;
always #* begin
case(Status)
2'b00: x = ... ;
2'b01: x = ... ;
2'b10: x = ... ;
2'b11: x = ... ;
endcase
end
x= (condition==2'b00)? a:(condition==2'b01)?:b:(condtion==2'b10)?:c:(condtion==2'b11)?:d
This is how your code looks when the values for assigning to x are replaced with a,b,c,d.The statement will definitely throw an error as you have clearly violated the way ternary operator is supposed to be used.
Ternary operator syntax:
x=(condition)?a:b
If the condition is true, x will be assigned the value of a.
If the condition is false, x will be assigned the value of b.
Ternary operator syntax if used in a nested way:
x=(condition1)?a:((condition2)?b:c)
If the condition1 is true, x will be assigned the value of a.
If the condition1 is false, it will check for condition2. If condition2 is true, x will be assigned the value of b else x will be assigned the value of c.
Looking at your code, you have repeated colons at inappropriate places.
x= (condition==2'b00)? a:(condition==2'b01)?:b:(condition==2'b10)?:c:(condition==2'b11)?:d
^ ^
There should not be a colon after the question mark.
Probably you can rewrite the condition as:
assign x= (condition==2'b00)?a:(condition==2'b01)? b:(condition==2'b10)?c:d;
Look at the small verilog code that helps in understanding the working of nested ternary operator:
Verilog code
Hope my code helps you!
You havent posted any specific error message.
A good way of Debugging :
Use $Display("any text") near line numbers that are pointed out as errors in the code by the compiler. From the code it seems you are doing a lot of Vector part Select. Case statement is a better choice.
Related
I am writing a piece of verilog code that negate a value. I expect if operand is signed, return its negative value and it is unsigned, return '1'.
Here is my code,
`define negation (a) ((a<0 || -a<0 || (a-1)<0) ? -a : 1)
Is there any fancy way to detect operand attributes?
There is no built-in attribute to check that an operand is signed. You could write your own attribute
let issigned(v) = (v|~v)<0;
Then use
let negation(a) = issigned(a) ? -a : 1;
You could do this with a text macro, but let is better to catch mistakes.
I have logic to compare a variable with multiple values.
For example:
logic [3:0] a;
always_comb begin
flag = (a == 'd13) || (a == 'd2) || (a=='d1); //can this be simplified?
end
Is there a easy way to write this statement?
This is more concise using the inside operator:
always_comb begin
flag = (a inside {1, 2, 13});
end
This is more scalable as well, allowing you to easily add or remove values from the set.
The syntax also supports ranges of values:
flag = (a inside {[1:2], 13});
Refer to IEEE Std 1800-2017, section 11.4.13 Set membership operator.
Since the values in the set are all constants, it should be synthesizable (but YMMV).
I am trying to understand some of the System Verilog syntax. I was struggling to finish an assignment and I came across this solution, but I do not understand why it works.
localparam int lo = w;
uwire [n:0] lo_bits, hi_bits;
assign answer = lo_bits == nlo ? lo_bits + hi_bits : lo_bits;
This is not exactly what I have in my code, but my question is the following: Why can't I rewrite this to a simple if-else block as such?
if (lo == lo_bits)
assign answer = lo_bits + hi_bits;
else
assign answer = lo_bits;
Verilog complains that lo_bits is a uwire and I cannot compare it with lo, but then why is it allowed in the example above? Aren't these two assignments equivalent?
Thank you very much for your help!
The difference is structural/declarative context versus procedural context. When you use an if clause in a declarative context (in this case it is at the same top level where you declare your wires and variables), it is considered a conditional generate construct (See Section 27.5 in the 1800-2017 LRM). This means the condition gets evaluated before simulation starts and must contain only constant expressions and no signals that can change during simulation. lo is a constant parameter, but not lo_bits.
If you want to use a procedural if, it needs to be inside a procedural block of code instantiated by always/initial blocks.
logic [n:0] answer;
always_comb
if (lo == lo_bits)
answer = lo_bits + hi_bits;
else
answer = lo_bits;
Computer Organization and Design (5th edition) by Hennessy and Patterson includes this Verilog code in Figure B.5.15 (p. B-37):
ALUOut <= A < B ? 1:0;
Is there any reason not to write this simpler statement instead:
ALUOut <= A < B;
In general, is there ever a reason to write "? 1 : 0" in Verilog?
The only people that can answer why they chose one way or the other are the authors. Many of the same people prefer to write if (expr != 0) instead if (expr). Maybe they come from VHDL and want to be more explicit.
The only reason I can think of why writing expression ? 1: 0 might be needed is when the expression evaluates to 'z and you want to convert it to 'x.
Say I have a scenario in which I need to compare only a few bits of a register and I don't care about other bits. eq, I need to check the first and last bits of a 3 bit register (A[2:0]) and I don't care about the middle bit, say compare vector is 3'b1X0 (Parameter).
Simplest way to do this is choose all the bits I care about, AND them and I have generated a control signal:
if ((A[2]==1) & ((A[0]==0)) Here the condition inside if statement is my control signal.
Another way is to use a casex statement: casex(A) begin 3'b1?0: ... , ... endcase.
Is there anything like ifx-elsex statement or something that can be used to do this kind of operation without using the 1st and 2nd method?
Thanks!
if (A[2:0] inside {3'b1?0} )
SystemVerilog keyword inside. It has been supported since at least Accellera's SystemVerilog 3.1 (before SystemVerilog was a part of IEEE). IEEE Std 1800-2012 11.4.13 has examples of use. inside is synthesizable.
There is also if ( A[2:0] ==? 3'b1?0 ) (IEEE Std 1800-2012 11.4.6). The only reference I have on hand (a book published 2004) says it is not supported for synthesis yet. You are welcome to try it.
(A[2]==1) is a logical expression the & is a bitwise operator, although either works it would be better semantics to use the && logical and operator. This is slightly different to most other languages where the && is a short-circuit operator.
Logically what you want is if ((A[2]==1) && ((A[0]==0)) but it could be reduced to a bitwise expression :
if ( ~A[0] & A[2] )
NB: Try to avoid using casex, the unknown parts will match x's in simulation. Try to use casez instead, ? can still be used to match don't cares.
Update comparing inside to casez
Case statements a clean control structure used in most languages to avoid large if elsif else chains. the inside operation will match x's to the do not care '?' values. this makes it usage similar to the casex which is considered to be bad practise to use as it can hide simulation fails.
casez(sel)
4'b1??? a= 3'd4;
4'b01?? a= 3'd3;
4'b001? a= 3'd2;
4'b0001 a= 3'd1;
4'b0000 a= 3'd0;
endcase
vs
if (sel inside {4'b1???})
a= 3'd4;
else if (sel inside {4'b01??})
a= 3'd3;
else if (sel inside {4'b001?})
a= 3'd2;
...
The above is actually equal to the casex (but more verbose) I believe that instead of casex you could also use :
case(sel) inside
4'b1??? a= 3'd4;
4'b01?? a= 3'd3;
4'b001? a= 3'd2;
4'b0001 a= 3'd1;
4'b0000 a= 3'd0;
endcase
but then I would never use a casex.
There's no operator I'm aware of that allows you to use '?' or 'x' inside an equality comparison to have them ignored.
Another alternative that you didn't mention would be to use a bitmask to select the bits you only care about. If you have a lot of bits this can be more compact than testing each bit individually.
If you only care about A == 3'b1?0, then it can be written as such:
if((A & 3'b101) == 3'b100)