I was trying to use the generate function in Verilog. The code compiled successfully, but it couldn't simulate. I get the following errors:
Illegal output or inout port connection for "port 'sum'".
Illegal output or inout port connection for "port 'carry'".
Could anyone tell me what am I doing wrong?
module test(input wire [2:0] a,
input wire [2:0] b,
output reg [2:0] s,
output reg [2:0] c);
genvar i;
generate
for(i=0;i<3;i=i+1)
adder_half inst(.sum(s[i]),.carry(c[i]),.a(a[i]),.b(b[i]));
endgenerate
endmodule
module adder_half(
output sum,carry,
input a,b
);
xor(sum,a,b);
and(carry,a,b);
endmodule
The reg type is only used for procedural assignments, but instance connections are treated more like continuous assignments.
Remove the reg keyword from your outputs. Change:
output reg [2:0] s,
output reg [2:0] c);
to:
output [2:0] s,
output [2:0] c);
Related
I am a student and new to verilog. I understand what these codes mean and they seem to be working for me. However, I am having troubles with the task.
module add_two_values_task(output reg sum,output reg cout, input ain,input bin);
task add_two_values;
output [3:0] sum;
output out;
input [3:0]ain;
input [3:0]bin;
reg [3:0] sum;
reg out;
{out, sum} = ain + bin;
endtask
always #(ain or bin) begin
add_two_values(cout,sum,ain,bin);
end
endmodule
However, when I run my simulation:
When I run the simulation, I suppose to get a value for z, however, I ended up with getting letter 'z' for the sum. Did I write my code wrong?
You just forgot about few very important syntax elements. And messed the order of arguments in your task.
module add_two_values_task(output reg [3:0] sum,output reg cout, input [3:0] ain, input [3:0] bin); // You need to declare signals width
task add_two_values;
output [3:0] sum;
output out;
input [3:0]ain;
input [3:0]bin;
reg [3:0] sum;
reg out;
{out, sum} = ain + bin;
endtask
always #(ain or bin) begin
add_two_values(sum,cout,ain,bin); // You messed order of arguments here
end
endmodule
Firstly in module declaration you need to declare bit width of input and output signals (otherwise signals will be assumed length of 1 bit). Secondly in your task call you messed order of arguments. Should work now.
Lets say I have a Verilog module with bit vector ports. How do I
instantiate it with some bits left unconnected?
I tried something like this but it didn't work:
module sub (in,out)
input [3:0] in;
output [3:0] out;
endmodule
module top;
wire [1:0] a1;
wire [1:0] c1;
sub Sub1(
.in[2:1](a1[1:0]),
.out[2:1](c1[1:0])
);
endomdule
It would be much easier to just declare signals of the correct size and use a continuous assignment
module top;
wire [1:0] a1;
wire [1:0] c1;
wire [3:0] pin;
wire [3:0] pout;
assign pin[2:1] = a1;
assign c1 = pout[2:1];
sub Sub1(
.in(pin),
.out(pout)
);
endomdule
In general, it is not a good idea to leave input ports floating. You could use a concatenation in the assignment, or directly in the port connection.
sub Sub1(
.in({1'b0,a1,1'b0}),
.out({pout[3],c1,pout[0]})
);
SystemVerilog has a net aliasing construct that makes thing even simpler
module top;
wire [3:0] pin;
wire [3:0] pout;
alias pin[2:1] = a1;
alias pout[2:1] = c1;
sub Sub1(
.in(pin),
.out(pout)
);
endomdule
Found LRM reference on why you cannot connect parts of ports.
LRM 1800-2012 Section 23.3.2.2 Connecting module instance ports by name:
The port_name shall be the name specified in the module declaration. The port name cannot be a bit-select, a part-select, or a concatenation of ports.
you cannot connect/disconnect parts of a port. You can do it with the whole port though. so, in your case you nedd to split your port in several parts, something like the following:
module sub (in1, in2, out1, out2);
input [2:1] in1;
input [1:0] in2;
output [2:1] out1;
output [1:0] out2;
endmodule
module top;
wire [1:0] a1;
wire [1:0] c1;
sub Sub1(
.in1(a1[1:0]),
.in2(),
.out1(c1[1:0]),
.out2()
);
endmodule
My code connect 4-bits to module's 8-bit outputs, upper/lower even middle part.
It does work, but what the hell is the 's'(or anything)?
It works in both Quartus Prime 18.0pro and Lattice Diamond 3.10(Symplify Pro).
module dff8
(
input clk,
input [7:0] a,
output reg [7:0] b
);
always # (posedge clk) begin
b <= a;
end
endmodule
module top
(
input clk,
input [7:0] x,
output [3:0] y,
output [3:0] z
);
dff8 u0 (.clk(clk), .a(x), .b({y,s,s,s,s}));
dff8 u1 (.clk(clk), .a(x), .b({s,s,s,s,z}));
endmodule
I have written the simple code below for a magnitude comparator. The 6 bits of C give the values of A=B,A!=B,etc; However, i am getting the following error when i run the code. How can i fix the error?
c2q39.v:7: error: C['sd5] is not a valid l-value in testbench.m.
c2q39.v:3: : C['sd5] is declared here as wire.
My code is
module mag(A,B,C);
input [3:0] A,B;
output [5:0] C;
always # (A or B)
assign C[5]=(A==B);
assign C[4]=(A!=B);
assign C[3]=(A>B);
assign C[2]=(A<B);
assign C[1]=(A>=B);
assign C[0]=(A<=B);
endmodule
module testbench;
reg [3:0] A,B;
wire [5:0] C;
mag m(A,B,C);
initial
begin
A=4'b0000;B=4'b0000;
#10 A=4'b1000;
#10 B=4'b1001;
#10 A=4'b1000;
end
initial
$monitor("%0d %b %b %b",$time,A,B,C);
endmodule
It is not a good idea to use assign statement in always block ( for more details refer here ). So you can define your output C as reg and implement the following way:
module mag(A,B,C);
input [3:0] A,B;
output reg [5:0] C;
always # (A or B)
begin
C[5]=(A==B);
C[4]=(A!=B);
C[3]=(A>B);
C[2]=(A<B);
C[1]=(A>=B);
C[0]=(A<=B);
end
endmodule
The other way to implement is just use assign statements.
module mag(A,B,C);
input [3:0] A,B;
output [5:0] C;
//always # (A or B)
assign C[5]=(A==B);
assign C[4]=(A!=B);
assign C[3]=(A>B);
assign C[2]=(A<B);
assign C[1]=(A>=B);
assign C[0]=(A<=B);
endmodule
My design needs multiple multiplexers, all of them have two inputs and most are 32 bits wide. I started with designing the 32 bit, 2:1 multiplexer.
Now I need a 5 bit, 2:1 multiplexer and I want to reuse my 32 bit design. Connecting the inputs is easy (see code below), but I struggle to connect the output.
This is my code:
reg [4:0] a, b; // Inputs to the multiplexer.
reg select; // Select multiplexer output.
wire [4:0] result; // Output of the multiplexer.
multiplex32_2 mul({27'h0, a}, {27'h0, b}, select, result);
When I run the code through iverilog, I get a warning that says that the multiplexer expects a 32 bit output, but the connected bus is only 5 bit wide. The simulation shows the expected results, but I want to get rid of the warning.
Is there a way to tell iverilog to ignore the 27 unused bits of the multiplexer output or do I have to connect a 32 bit wide bus to the output of the multiplexer?
I don't know of a #pragma or something like that (similar to #pragma argsused from C) that can be used in Verilog.
Xilinx ISE, for example, has a feature called "message filtering", which allows the designer to silence specific warning messages. You find them once, select them, choose to ignore, and subsequent synthesis won't trigger those warnings.
Maybe you can design your multiplexer in a way you don't need to "waste" connections (not actually wasted though, as the synthesizer will prune unused connections from the netlist). A more elegant solution would be to use a parametrized module, and instantiate it with the required width. Something like this:
module mux #(parameter WIDTH=32) (
input wire [WIDTH-1:0] a,
input wire [WIDTH-1:0] b,
input wire sel,
output wire [WIDTH-1:0] o
);
assign o = (sel==1'b0)? a : b;
endmodule
This module has been tested with this simple test bench, which shows you how to instantiate a module with params:
module tb;
reg [31:0] a1,b1;
reg sel;
wire [31:0] o1;
reg [4:0] a2,b2;
wire [4:0] o2;
mux #(32) mux32 (a1,b1,sel,o1);
mux #(5) mux5 (a2,b2,sel,o2);
// Best way to instantiate them:
// mux #(.WIDTH(32)) mux32 (.a(a1),.b(b1),.sel(sel),o(o1));
// mux #(.WIDTH(5)) mux5 (.a(a2),.b(b2),.sel(sel),.o(o2));
initial begin
$dumpfile ("dump.vcd");
$dumpvars (1, tb);
a1 = 32'h01234567;
b1 = 32'h89ABCDEF;
a2 = 5'b11111;
b2 = 5'b00000;
repeat (4) begin
sel = 1'b0;
#10;
sel = 1'b1;
#10;
end
end
endmodule
You can test it yourself using this Eda Playground link:
http://www.edaplayground.com/x/Pkz
I think the problem relates to the output of the multiplexer which is still 5 bits wide. You can solve it by doing something like this:
reg [4:0] a, b; // Inputs to the multiplexer.
reg select; // Select multiplexer output.
wire [31:0] temp;
wire [4:0] result; // Output of the multiplexer.
multiplex32_2 mul({27'h0, a}, {27'h0, b}, select, temp);
assign result = temp[4:0];
This can be easily tested in http://www.edaplayground.com/ using the code below:
( I have re-used #mcleod_ideafix's code)
// Code your testbench here
// or browse Examples
module mux #(parameter WIDTH=32) (
input wire [WIDTH-1:0] a,
input wire [WIDTH-1:0] b,
input wire sel,
output wire [WIDTH-1:0] o
);
assign o = (sel==1'b0)? a : b;
endmodule
module tb;
reg [31:0] a,b;
wire [31:0] o;
wire [4:0] r;
reg sel;
initial begin
$dumpfile("dump.vcd"); $dumpvars;
a = 10; b = 20; sel = 1;
end
mux MM(a,b,sel,o);
assign r = o[4:0];
endmodule
Let me know if you are still getting a warning.
Why do we have to take the same variable name of an output and also wire for getting the value? eg:
module TEST(INP1,INP2,CIN,COUT,SUM);
input [31:0] INP1;
input [31:0] INP2;
output [31:0] SUM;
input CIN;
output COUT;
wire [31:0] SUM;// Again redefined
wire COUT; // Again Redefined
assign {COUT,SUM} = INP1 + INP2 + CIN ;
Example for getting the Carry-out and the Sum of two numbers and Carry-In taken as the input.
Verilog 1995 did require the port direction to be listed after. Output wire types were implicit and regs could be declared inline with direction.
module TEST(A,B,C,D);
input [31:0] A;
input [31:0] B;
output [31:0] C;
output D;
reg D;
could be written as:
module TEST(A,B,C,D);
input [31:0] A;
input [31:0] B;
output [31:0] C;
output reg D; //Only declared twice
Since Verilog 2001 the extra definition is no longer required and they can be declared inline (ANSI-Style).
module TEST(
input [31:0] A,
input [31:0] B,
output [31:0] C,
output reg D // Declared Once
);
From SystemVerilog (2009) we have the logic type, you no longer have to switch between reg and wire types. The only requirement is that if you need to tri-state use wire or tri.
module TEST(
input [31:0] A,
input [31:0] B,
output logic [31:0] C,
output logic D
);
My understanding of the original requirement for having reg and wire types was for simulation speed or ease of simulator design. The value of a wire is evaluated every simulation delta cycle while a reg is only evaluated when triggered by the sensitivity list.
It is not necessary to declare an output also as a wire. Furthermore, you can avoid duplicating the port list by using ANSI-stlye port declarations:
module TEST (
input [31:0] INP1,
input [31:0] INP2,
output [31:0] SUM,
input CIN,
output COUT
);
assign {COUT,SUM} = INP1 + INP2 + CIN ;
endmodule
In your example, you do not need to declare outputs as reg. But, if you need to for another circuit, you can declare the type on the same line, such as:
output reg [31:0] Q;
Because just declaring a net as output doesn't describe if it is a reg type or a wire type.
An output can either be driven by a wire or reg, you have to tell it what type the driver is going to be.