So I've already got my triangle waveforms, now i want to change the frequency of it, but i'm getting errors and i don't know what's the actual problem.
module sxoc(clk,res,out1,freq,count);
input clk,res;
input [0:7]freq;
output [0:7]count;
output [0:7]out1;
reg [0:7]out1;
always #(posedge clk)
begin
if (res)
begin
out1=8'b00000000;
count=8'b00000000;
end
else
count =count + 1;
if (count == freq)
if(out1<=256)
begin
out1=out1 + 1;
count = 0;
end
end
endmodule
module atam_test;
reg clk,res;
reg [0:7]freq;
wire [0:7]count;
wire [0:7]out1;
sxoc sxoc1(clk,res,out1,freq,count);
always #2 clk=~clk;
initial
begin
clk=0;res=1;freq=8'b00000011;
#5 res=0;
end
initial #5000 $finish;
endmodule
Procedural assignments (in an always block) can only be made to a reg. Change:
output [0:7]count;
to:
output reg [0:7]count;
Related
I have a text file with hexadecimal data. I want to display the data at only the positive edge of the clock, thus controlling the frequency of the data. I have written the following code:
module testbench;
reg [15:0] in[0:5];
reg clk;
integer i;
initial
clk=1'b0;
always
#5 clk = ~clk;
initial
$readmemh("Input_rsvd.dat",in);
always # (posedge clk)
begin
for(i=0;i<5;i=i+1)
$display( "result = %h",in);
end
endmodule
Obviously, the code has some problem which I can not figure out. Can anybody help me with this?
When I try to run your code, I get a compile error on multiple simulators. You can not pass a memory variable to $display like that. I think you intended to print one value at a time. To fix it, change:
$display( "result = %h",in);
to:
$display( "result = %h",in[i]);
Also, if you want to print all 6 values, change:
for(i=0;i<5;i=i+1)
to:
for(i=0;i<6;i=i+1)
Here is the new code, using a more consistent layout:
module testbench;
reg [15:0] in [0:5];
reg clk;
integer i;
initial clk = 1'b0;
always #5 clk = ~clk;
initial $readmemh("Input_rsvd.dat", in);
always #(posedge clk) begin
for (i=0; i<6; i=i+1) $display("result = %h", in[i]);
end
endmodule
module rff_try_1(q,inp,clk);
input clk,inp;
output q;
reg q;
DFF dff0(q,inp,clk);
endmodule
module DFF(q,inp,clk);
input inp,clk;
output q;
reg q;
always # (posedge clk)begin
if(clk)begin
q=inp;
end
end
endmodule
here I'm using two modules but output is not coming
I'm trying to make two bit right shift register but 1st i have to make one single bit register but even this is not working
There are several mistakes in the code.
1) The line if(clk)begin and relevant end should be removed, posedge clk already describes trigger condition of the flip-flop.
2) A non-blocking assignment (<=) is required for the sequential logic.
The always block should be as follows:
always # (posedge clk) begin
q <= inp;
end
3) Some simulators don't complain, but signal q should be wire in module rff_try_1.
wire q;
Simulation
I simulated the code (after the modifications) on EDA Playground with the testbench below. Used Icarus Verilog 0.9.7 as simulator.
module tb();
reg clk = 1;
always clk = #5 ~clk;
reg inp;
wire q;
rff_try_1 dut(q, inp, clk);
initial begin
inp = 0;
#12;
inp = 1;
#27;
inp = 0;
#24;
inp = 1;
end
initial begin
$dumpfile("dump.vcd"); $dumpvars;
#200;
$finish;
end
endmodule
The signal q is as expected as seen on the waveform.
I'm writing a verilog code where i'm reading two files and saving those numbers into registers. I'm then multiplying them and adding them. Pretty much a Multiplication Accumulator. However i'm having a hard frustrating time with the code that i have. It read the numbers from the files correctly and it multiples but here is the problem? When i first run it using ModelSim, I reset everything so i can clear out the accumulator. I then begin the program, but there is always this huge delay in my "macc_out" and i cannot seem to figure out why. This delay should not be there and instead it should be getting the result out A*B+MAC. Even after the delay, it's not getting the correct output. My second problem is that if i go from reset high, to low (start the program) and then back to reset high ( to reset all my values), they do not reset! This is frustrating since i've been working on this for a week and don't know/can't see a bug. Im asking for an extra set of eyes to see if you can spot my mistake. Attached is my code with the instantiations and also my ModelSim functional Wave Form. Any help is appreciated!
module FSM(clk,start,reset,done,clock_count);
input clk, start, reset;
output reg done;
output reg[10:0] clock_count;
reg [0:0] macc_clear;
reg[5:0] Aread, Bread, Cin;
wire signed [7:0] a, b;
wire signed [18:0] macc_out;
reg [3:0] i,j,m;
reg add;
reg [0:0] go;
reg[17:0] c;
parameter n = 8;
reg[1:0] state;
reg [1:0] S0 = 2'b00;
reg [1:0] S1 = 2'b01;
reg [1:0] S2 = 2'b10;
reg [1:0] S3 = 2'b11;
ram_A Aout(.clk(clk), .addr(Aread), .q(a));
ram_B Bout(.clk(clk), .addr(Bread), .q(b));
mac macout(.clk(clk), .macc_clear(macc_clear), .A(a), .B(b), .macc_out(macc_out), .add(add));
ram_C C_in(.clk(clk), .addr(Cin), .q(c));
always #(posedge clk) begin
if (reset == 1) begin
i <= 0;
add<=0;
j <= 0;
m <= 0;
clock_count <= 0;
go <= 0;
macc_clear<=1;
end
else
state<=S0;
case(state)
S0: begin
// if (reset) begin
// i <= 0;
// add<=0;
// j <= 0;
// m <= 0;
// clock_count <= 0;
// go <= 0;
// macc_clear<=1;
// state <= S0;
// end
macc_clear<=1;
done<=0;
state <= S1;
end
S1: begin
add<=1;
macc_clear<=0;
clock_count<=clock_count+1;
m<=m+1;
Aread <= 8*m + i;
Bread <= 8*j + m;
if (m==7) begin
state <= S2;
macc_clear<=1;
add<=0;
end
else
state <=S1;
end
S2: begin
add<=1;
macc_clear<=0;
m<=0;
i<=i+1;
if (i<7)
state<=S1;
else if (i==8) begin
state<=S3;
add<=0;
end
end
S3: begin
add<=1;
i<=0;
j<=j+1;
if(j<7)
state<=S1;
else begin
state<=S0;
done<=1;
add<=0;
end
end
endcase
end
always # (posedge macc_clear) begin
Cin <= 8*j + i;
c <= macc_out;
end
endmodule
module mac(clk, macc_clear, A, B, macc_out, add);
input clk, macc_clear;
input signed [7:0] A, B;
input add;
output reg signed [18:0] macc_out;
reg signed [18:0] MAC;
always #( posedge clk) begin
if (macc_clear) begin
macc_out <= MAC;
MAC<=0;
end
else if (add) begin
MAC<=(A*B)+ MAC;
macc_out<=MAC;
end
end
endmodule
module ram_A( clk, addr,q);
output reg[7:0] q;
input [5:0] addr;
input clk;
reg [7:0] mem [0:63];
initial begin
$readmemb("ram_a_init.txt", mem);
end
always #(posedge clk) begin
q <= mem[addr];
end
endmodule
module ram_C(clk,addr, q);
input [18:0] q;
input [5:0] addr;
input clk;
reg [18:0] mem [0:63];
always #(posedge clk) begin
mem[addr] <= q;
end
endmodule
ModelSim Functional Simulation Wave Form
1) Take a look at the schematic view for your MACC module - I think some of your "problems" will be obvious from that;
2) Consider using an always#(*) (Combinational) block for your FSM control signals (stuff like add or macc_clear) rather than a always#(posedge clk) (sequential) - it makes the logic to assert them easier. Right now they're registered, so you have a cycle delay. ;
3) In your MAC, you clear the MAC register on a reset, but you don't clear the macc_out register.
In short, I think you need to step back, and consider which signals are combinational logic, and which ones are sequential and need to be in registers.
i am unable to get correct output in a text file however simulation in modelsim is quite ok.. but while writing it to text file im getting XX for every input. may be there is some syntax error or some other. if any can help plz write down test bench for writing dout (output )of a flipflop (as an example) with every dout(output) showing in a new line in a text file.
Code:
module LFSR( clk,reset,out);
parameter width =4;
input clk,reset;
output [width-1:0] out ;
reg [width-1:0] lfsr;
integer r;
wire feedback = lfsr[width-1]^lfsr[width-2];
always #(posedge clk)
if (reset)
begin
lfsr <= 4'b1000;
end
else
begin
lfsr[0] <= feedback;
for(r=1;r<width;r=r+1)
lfsr[r]<=lfsr[r-1];
end
assign out=lfsr;
endmodule
Testbench:
module aaatest();
parameter width =4;
reg clk,reset;
wire [width-1:0] out;
reg [width-1:0] lfsr[13:0];
integer f,i;
initial
begin
f = $fopen("output.txt","w");
end
LFSR patt (clk,reset,out);
always #5 clk=~clk;
initial begin
clk=1; reset=1;
#10 reset=0;
# 140 $stop;
end
initial
begin
clk=1;
for (i = 0; i<14; i=i+1)
#(posedge clk)
lfsr[i]<= out;
end
initial begin
for (i = 0; i<14; i=i+1)
$fwrite(f,"%b\n",lfsr[i]);
end
initial begin
$display("clk out");
$monitor("%b,%b", clk, out);
end
initial
begin
$fclose(f);
end
endmodule
I would like you to think about these sections of code:
initial begin
f = $fopen("output.txt","w");
end
initial begin
for (i = 0; i<14; i=i+1)
$fwrite(f,"%b\n",lfsr[i]);
end
initial begin
$fclose(f);
end
When describing hardware we have a massively parallel simulation. All initials are meant to start at the same time, time 0.
If this works at all, as there is no guarantee that the file will be opened before you write to it, you are writing the file at time zero before you have even reset the logic your simulating.
Something like below might be more appropriate:
initial begin
f = $fopen("output.txt","w");
#(negedge reset); //Wait for reset to be released
#(posedge clk); //Wait for fisrt clock out of reset
for (i = 0; i<14; i=i+1) begin
$fwrite(f,"%b\n",lfsr[i]);
end
$fclose(f);
end
To follow up on Gregs suggestions the reset being released too early consider something similar to:
initial begin
clk=0; reset=1; //Clock low at time zero
#(posedge clk);
#(posedge clk);
reset=0;
# 140 $stop;
end
Which keep reset asserted for 2 clock rising edges.
Update with working example
There are a few odd things happening, you call $stop (Not $finish) after #140 but also try to loop 14 times, the $stop means only 4 loops are executed.
Your test program is made up of 2 initial begins working in parallel rather than one program that is sequentially executed. You had no delay in writing out your text file and you wrote the buffered version of the lfsr rather than the lfsr output directly.
The following example simulates correctly and writes the text file your looking for:
module aaatest();
parameter width =4;
reg clk,reset;
wire [width-1:0] out;
reg [width-1:0] lfsr[13:0];
integer f,i;
LFSR patt (clk,reset,out);
always #5 clk=~clk;
//Clock and reset release
initial begin
clk=0; reset=1; //Clock low at time zero
#(posedge clk);
#(posedge clk);
reset=0;
end
initial begin
f = $fopen("output.txt","w");
#(negedge reset); //Wait for reset to be released
#(posedge clk); //Wait for fisrt clock out of reset
for (i = 0; i<14; i=i+1) begin
#(posedge clk);
lfsr[i] <= out;
$display("LFSR %b", out);
$fwrite(f,"%b\n", out);
end
$fclose(f);
$finish;
end
endmodule
My code for the design block and the testbench compiles; however, when I simulate, I'm not getting the correct output. Can anyone tell me where I'm going wrong in my code?
Here is the code for testbench:
module testbench;
reg [511:0]FROM_LS;
reg CLK;
reg [63:0]TO_IF_ID;
initial
begin
CLK= 0;
TO_IF_ID[63:0]=63'b0;
FROM_LS[511:480]= 32'b00011_00000_00100_01100_11100_10111_01;
FROM_LS[479:448]=32'b00_11000_00100_01111_11111_00011_10000;
end
always
begin
#10 CLK= ~ CLK;
//FROM_LS[511:448]= ~ FROM_LS[511:448];
$display("FROM_LS= %b", FROM_LS);
$display("TO_IF_ID= %b", TO_IF_ID);
end
endmodule
and here is the code for the design block:
module inst_line_buffer(input wire [511:0]from_LS,
input wire clk,
output reg [63:0]to_if_id);
parameter mem_size=16;
integer k;
reg [31:0] ilb[0:mem_size-1];
initial
begin
for (k = 0; k < mem_size ; k = k + 1)
begin
ilb[k] = 32'b00;
//$display ("ilb= %b",ilb[k]);
end
end
always #(posedge clk)
begin
ilb[0]= from_LS[511:480];
ilb[1]= from_LS[479:448];
ilb[2]= from_LS[447:416];
ilb[3]= from_LS[415:384];
ilb[4]= from_LS[383:352];
ilb[5]= from_LS[351:320];
ilb[6]= from_LS[319:288];
ilb[7]= from_LS[287:256];
ilb[8]= from_LS[255:224];
ilb[9]= from_LS[223:192];
ilb[10]= from_LS[191:160];
ilb[11]= from_LS[159:128];
ilb[12]= from_LS[127:96];
ilb[13]= from_LS[95:64];
ilb[14]= from_LS[63:32];
ilb[15]= from_LS[31:00];
to_if_id [63:32]= ilb[0];
to_if_id [31:0]= ilb[1];
$display("ilb= %b", ilb[1]);
end
endmodule
I'm expecting that the value of TO_IF_ID should be 0001100000001000110011100101110100110000010001111111110001110000, but I'm getting all zeros.
When you run a simulation on your testbench module, TO_IF_ID is always 0 because you only assigned a value to it once at time 0 in your initial block. If you want the value to change, it needs to be driven somehow.
As Andy pointed out in a comment, you probably meant to instantiate the inst_line_buffer module in your testbench. Verilog will not do this magically for you. But then, you should declare TO_IF_ID as a wire instead of a reg and remove it from the initial block.
module testbench;
reg [511:0]FROM_LS;
reg CLK;
wire [63:0]TO_IF_ID;
inst_line_buffer inst_line_buffer (
.from_LS (FROM_LS),
.clk (CLK),
.to_if_id (TO_IF_ID)
);
initial begin
CLK= 0;
FROM_LS[511:480]= 32'b00011_00000_00100_01100_11100_10111_01;
FROM_LS[479:448]=32'b00_11000_00100_01111_11111_00011_10000;
#500 $finish;
end
always
begin
#10 CLK= ~ CLK;
//FROM_LS[511:448]= ~ FROM_LS[511:448];
$display("FROM_LS= %b", FROM_LS);
$display("TO_IF_ID= %b", TO_IF_ID);
end
endmodule