Hi i am using the folowing code to design a n-bit counter.
Depending on the start and end i want to instantiate up or down counter.
But i am getting "Malformed statement". Please help.
module nbitUpCounter(startc,endc , clk, rst_n,actlow,count);
parameter n = 7;
output reg [n:0] count;
input [n:0] startc;
input [n:0] endc;
input clk;
input rst_n;
input actlow;
// Increment count on clock
always #(actlow or posedge clk or negedge rst_n)
begin
if (actlow == 0)
begin
if (rst_n==0)
count = startc;
else if (count==endc) count=startc;
else count = count + 1;
end
end
endmodule
module nbitDownCounter(startc,endc , clk, rst_n,actlow,count);
parameter n = 7;
output reg [n:0] count;
input [n:0] startc;
input [n:0] endc;
input clk;
input rst_n;
input actlow;
// Increment count on clock
always #(actlow or posedge clk or negedge rst_n)
begin
if (actlow == 0)
begin
if (rst_n==0)
count = startc;
else if (count==endc) count=startc;
else count = count - 1;
end
end
endmodule
module Init(startc,endc , clk, rst_n,actlow,count);
parameter n = 7;
output wire [n:0] count;
input [n:0] startc;
input [n:0] endc;
input clk;
input rst_n;
input actlow;
generate
initial
begin
if(startc>endc)
nbitDownCounter c(startc, endc, C_t,rst_t,actlow,count);
end
endgenerate
endmodule
module Testbench;
reg [7:0] startc, endc;
reg C_t, rst_t;
reg actlow;
wire [7:0] outc;
initial
begin
//case 0
startc <= 8'b00000011; endc <= 8'b0000001;
//Init i(startc,endc,C_t,rst_t,actlow,count);
actlow<=0;
C_t <=1; rst_t <=0;
#1 $display("count = %b",outc );
//case1
rst_t<=1;C_t<=0;C_t<=1;
#1 $display("count = %b",outc );
//Case3
C_t<=0;C_t<=1;
#1 $display("count = %b",outc );
//Case3
C_t<=0;C_t<=1;
#1 $display("count = %b",outc );
end
endmodule
You're trying to instantiate your module in an initial block, which is illegal. Removing the initial begin inside module Init should solve the problem. Have a look at this page for an example: http://asic-soc.blogspot.de/2012/06/verilog-hdl-generate-blocks.html
Related
This is the verilog code for mod 64 counter, incrementing every clock cycle
module modulus64counter
#(parameter N=64,
parameter WIDTH=5)
(input clk,
input rstn,
output reg[WIDTH-1:0] out);
integer i;
always #(posedge clk) begin
if(!rstn) begin
out<=0;
end
else begin
if(out==N-1)
out<=0;
else
out<= out+1;
end
end
endmodule
and the test bench is
module modulus64countertb;
// Inputs
reg clk;
reg rstn;
// Outputs
wire [4:0] out;
// Instantiate the Unit Under Test (UUT)
modulus64counter uut (
.clk(clk),
.rstn(rstn),
.out(out)
);
always #10 clk = ~clk;
initial begin
// Initialize Inputs
clk = 1;
rstn = 0;
$monitor ("T=%0t rstn=%0b out=0X%h", $time,rstn,out);
repeat(2) #(posedge clk);
rstn <=1;
repeat(50) #(posedge clk);
$finish;
end
endmodule
Now if i want to increment the value of out every "n" clock cycle instead of consecutive clock cycle , how can i modify the program
Kindly help
Updated 20220131
Updated the code to produce output after every 2 clock cycles. Similarly, if you wish to delay for even more clock cycle, the simplest way is to continuously flopping it.
For a better implementation, you can try out a shift register.
module modulus64counter #(
parameter N=64,
parameter WIDTH=8,
parameter DELAY_CYCLE=2
)(
input clk,
input rstn,
output reg[WIDTH-1:0] out,
output reg[WIDTH-1:0] actual_out
);
integer i;
reg [WIDTH-1:0] cntr;
reg [WIDTH-1:0] dly1clk;
always #(posedge clk) begin
if(!rstn) begin
out <= 0;
dly1clk <= 0;
end else if(out == DELAY_CYCLE-1) begin
out <= 0;
dly1clk <= dly1clk + 1;
end else begin
out <= out + 1;
end
end
always #(posedge clk) begin
if(!rstn) begin
actual_out <= 0;
end else begin
actual_out <= dly1clk;
end
end
endmodule
The code below should work for you. You can always swap the out and actual_out if you insist on using out as the final counting variable.
Also, removing the out on the monitor line in the testbench will only print the value when it reaches mod n. I kept both out and actual_out on testbench's monitor to ease debugging purpose.
Verilog code
module modulus64counter #(
parameter N=64,
parameter WIDTH=8
)(
input clk,
input rstn,
output reg[WIDTH-1:0] out,
output reg[WIDTH-1:0] actual_out
);
integer i;
reg [WIDTH-1:0] cntr;
always #(posedge clk) begin
if(!rstn) begin
out <= 0;
actual_out <= 0;
end else if(out == N-1) begin
out <= 0;
actual_out <= actual_out + 1;
end else begin
out <= out + 1;
end
end
endmodule
Testbench
module modulus64countertb;
// Inputs
reg clk;
reg rstn;
// Outputs
wire [7:0] out;
wire [7:0] actual_out;
// Instantiate the Unit Under Test (UUT)
modulus64counter uut (
.clk(clk),
.rstn(rstn),
.out(out),
.actual_out(actual_out)
);
always #10 clk = ~clk;
initial begin
// Initialize Inputs
clk = 1;
rstn = 0;
$monitor ("T=%0t rstn=%0b out=%d actual_out=%d", $time,rstn,out,actual_out);
repeat(2) #(posedge clk);
rstn <=1;
repeat(200) #(posedge clk);
$finish;
end
endmodule
Output result simulated using edaplayground:
I am trying to assign ADDR to pcOut but ADDR is showing up as xxxxxxxx in GTKWave.
Here is my code:
module processor (
input CLK,
// Memory
input [31:0] DATAOUT, // Memory data out
output [31:0] DATAIN, // Memory data in
output [31:0] ADDR, // Memory address
output WE // Memory write enable
);
wire [3:0] aluSel;
wire [4:0] regSel1, regSel2, regDataSel;
wire regLoad, aluEnable, pcLoad, pcNext;
wire [31:0] regDataIn, regDataOut1, regDataOut2, aluOut, pcOut, pcIn, aluA, aluB;
assign ADDR = pcOut;
controlUnit controlUnit (
.CLK(CLK), // Clock
// Outputs
.memDataOut(DATAOUT),
.regDataOut1(regDataOut1),
.regDataOut2(regDataOut2),
.aluOut(aluOut),
.pcOut(pcOut),
// Load and enable
.pcLoad(pcLoad),
.regLoad(regLoad),
.aluEnable(aluEnable),
.pcNext(pcNext),
// Selects
.aluSel(aluSel),
.regSel1(regSel1),
.regSel2(regSel2),
.regDataSel(regDataSel),
// Inputs
.pcIn(pcIn),
.regDataIn(regDataIn),
.aluA(aluA),
.aluB(aluB),
.memDataIn(DATAIN),
.memAddr(ADDR)
);
datapath datapath (
.pcNext(pcNext),
// Load and enable
.pcLoad(pcLoad),
.regLoad(regLoad),
.aluEnable(aluEnable),
// Selects
.aluSel(aluSel),
.regSel1(regSel1),
.regSel2(regSel2),
.regDataSel(regDataSel),
// Inputs
.regDataIn(regDataIn),
.pcIn(pcIn),
.aluA(aluA),
.aluB(aluB),
// Outputs
.regDataOut1(regDataOut1),
.regDataOut2(regDataOut2),
.aluOut(aluOut),
.pcOut(pcOut)
);
endmodule
Can anyone help?
Thanks in advance.
Edit:
pcOut is outputting the correct value but ADDR is not being set that same value.
Edit 2:
Here is the code for the controlUnit module:
module controlUnit (
input CLK,
input [31:0] memDataOut, regDataOut1, regDataOut2, aluOut, pcOut,
output reg [0:0] pcLoad, regLoad, aluEnable, pcNext,
output reg [3:0] aluSel,
output reg [4:0] regSel1, regSel2, regDataSel,
output reg [31:0] pcIn, regDataIn, aluA, aluB, memDataIn, memAddr
);
reg cycle = 0;
wire [10:0] opcode;
wire [4:0] rs1, rs2, rd;
decoder decoder (
.cycle(cycle),
.instruction(memDataOut),
.rs1(rs1),
.rs2(rs2),
.rd(rd),
.opcode(opcode)
);
always #(posedge CLK) begin
case (cycle)
1'b0: begin
regLoad <= 0;
aluEnable <= 0;
pcNext <= 0;
end
1'b1: begin
pcNext <= 1;
case (opcode)
11'b00000110011: begin // Add
regSel1 <= rs1;
regSel2 <= rs2;
regDataSel <= rd;
aluSel <= 0;
aluEnable <= 1;
regDataIn <= aluOut;
regLoad <= 1;
end
11'b10000110011: begin // Sub
end
endcase
end
endcase
cycle <= !cycle;
end
endmodule
Your controlUnit doesn't seem to have any logic attached to memAddr, but memAddr is still an output of controlUnit. At the top level, you port map ADDR to .memAddr, and you also assign ADDR = pcOut. You're trying to drive ADDR in two different locations.
parameter N1 = 5;
parameter N2 = 5;
wire [(N1+N2-1):0] seckey [8:1];
shiftreg #(.depth(N1+N2-1)) sr1( .clk(clk), .reset(reset), .data_in(muxout[1]), .data_out(seckey[0]));
//--------------------------------------------------------------------------//
module shiftreg(
input clk,
input reset,
input data_in,
output data_out
);
parameter depth = 9;
wire [depth:0] connect_wire;
wire [depth:0] data_out;
//wire [depth:0] data_out;
assign connect_wire[0] = data_in;
assign data_out[depth:0] = connect_wire[depth:0];
genvar i;
generate
for(i=1; i<=depth; i=i+1) begin: loop1
ff dff(.d(connect_wire[i-1]), .clk(clk), .reset(reset), .q(connect_wire[i]));
end
endgenerate
endmodule
//--------------------------------------------------------------------//
module ff(
input d,
input clk,
input reset,
output reg q
);
always # (posedge clk or posedge reset)
begin
if (reset) begin
q <= 1'b0;
end
else begin
q <= d;
end
end
endmodule
//------------------------------------------------------------------------//
Value of N1 and N2 is 5.
I am getting the error "Size mismatch in connection of port (data_out). Formal port size is 10-bit while actual signal size is 1-bit"
I have set the size of the data_out port to be 10 bits but its still showing the signal size to be 1 bit.
To set the size of data_out, you need to set the size where you declare the parameter. Try the header below
module shiftreg(clk, reset, data_in, data_out);
parameter depth = 9;
input clk;
input reset;
input data_in;
input [depth:0] data_out;
Also:
assign data_out[depth:0] = connect_wire[depth:0];
can be replaced with
assign data_out = connect_wire;
I'm trying to calculate times in which input x with 8 bits is repeated on every posedge clk.
I'm thinking about creating 256b counter to each value of these 8 bit to compare x with it, but I get error when I'm trying to compare each value of these counter with each input x on rising edge.
module counter_initial(x);
input[7:0] x;
//output [7:0] y;
//reg [7:0] y;
//reg [7:0] freq_tst,gap_tst;
reg [7:0] freq_num;
endmodule
module counter_256(clk,x,out);
input [7:0] x;
input clk;
// input [7:0] in;
output [7:0] out;
reg [7:0] out;
//reg [7:0] freq_tst,gap_tst;
reg [7:0] k=0;
// reg [] t=0;
genvar i;
generate
for (i=0;i<256;i=i+1)
begin
counter_initial m(i);
//t=m(i);
end
endgenerate
always #(posedge clk)
begin
if(k<256) begin
if (x==m[i])
//counter_initial[k]==x
begin
freq_num=freq_num+1;
end
//else
//begin gap_tst=gap_tst+1; end
k=k+1;
end
end
endmodule
You don't need an additional module to count. You can use a memory array. Example:
input [WIDTH-1:0] x;
reg [7:0] mem [WIDTH-1:0];
integer i;
always #(posedge clk) begin
if (reset) begin
for (i = 0; i < 2**WIDTH; i = i+1) begin
mem[i] <= 8'b0;
end
end
else if (mem[x] < 8'd255) begin // cap counting and prevent overflow
mem[x] <= mem[x] + 1'b1;
end
end
If you want to use separate modules then pass the clock to it. Example:
module counter (output reg [7:0] count, input increment, clk, reset);
always #(posedge clk) begin
if (reset) begin
count <= 8'b0;
end
else if (count < 8'd255) begin // cap counting and prevent overflow
count <= count + increment;
end
end
endmodule
module my_device ( /* ..., */ input [7:0] x, input clk, reset );
/* ... */
genvar i;
generate
for (i=0; i<256; i=i+1) begin
counter icount( .count(/* ... */), .increment(x==i), .* );
end
endgenerate
/* ... */
endmdoule
Reminder 8'd255 + 1 is 8'd0 because the MSB of 8'd256 is out of range. I capped the counters so the will not overflow and roll back to zero.
I have the following verilog code. Idea is to store value of counter at the time of reset. However, I am not sure if it would be synthesizable(memories need synchronous reset). I get DRC violatins and the memory, bufreadaddr, bufreadval are all optimized out. What are some other ways to write this?
module counter (clk,reset, d_out,laststoredvalue, bufreadaddr, bufreadval, resetcount) ;
input clk ,reset ;
input [5:0] resetcount;
output [15:0] d_out;
output [15:0] laststoredvalue;
input [5:0] bufreadaddr;
output [15:0] bufreadval;
reg [15:0] bufreadval;
reg [15:0] laststoredvalue;
reg [15:0] d_out;
reg [15:0] d_out_mem[63:0];
always #(negedge reset or posedge clk) begin
if (reset == 0) begin
d_out <= 16'h0000;
d_out_mem[resetcount] <= d_out;
laststoredvalue <= d_out;
end else begin
d_out <= d_out + 1'b1;
end
end
always #(bufreadaddr)
bufreadval = d_out_mem[bufreadaddr];
integer count;
initial begin
count = 0;
end
always #(posedge clk ) begin
count = count + 1;
//$display(count);
end
endmodule
hi i have made a small change for your code; added a temporary variable to store the output in a register it will store previous value on reset;
module counter (clk,reset, d_out,laststoredvalue, bufreadaddr, bufreadval, resetcount) ;
input clk ,reset ;
input [5:0] resetcount;
output [15:0] d_out;
output [15:0] laststoredvalue;
input [5:0] bufreadaddr;
output [15:0] bufreadval;
reg [15:0] bufreadval;
reg [15:0] laststoredvalue;
reg [15:0] temp;
reg [15:0] d_out;
reg [15:0] d_out_mem[63:0];
always #(negedge reset or posedge clk) begin
if (reset == 0) begin
d_out_mem[resetcount] = d_out;
laststoredvalue = temp;
d_out = #10 16'h0000;
end
else begin
d_out = d_out + 1'b1;
temp = d_out;
end
end
always #(bufreadaddr)
bufreadval = d_out_mem[bufreadaddr];
endmodule
remaining code is same as it is.