For a very strange reason (scripts we use) I need to be able to declare a localparam AFTER I declare wires and regs in a module:
module blah (clk, rst, in, out);
input clk;
input rst;
input [2:0] in;
output [3:0] out;
wire res;
localparam NUMBER=5;
...
is this legal verilog code? I would also appreciate a link to the relevant seciton in the documentation. Thanks!
This is valid Verilog (2001). Verilog 2001 saw the introduction of localparam, for all versions it is still syntactically valid to use parameter in this context. localparam indicates that it can not be overridden.
Usage can be seen in section 23.10 Overriding module parameters of SystemVerilog IEEE Std 1800-2012.
From IEEE 1800-2012:
For example:
module generic_fifo
#(MSB=3, LSB=0) // parameter port list parameters
(input wire [MSB:LSB] in,
input wire clk, read, write, reset,
output logic [MSB:LSB] out,
output logic full, empty );
parameter DEPTH=4; // module item parameter
localparam FIFO_MSB = DEPTH*MSB;
localparam FIFO_LSB = LSB;
// These constants are local, and cannot be overridden.
// They can be affected by altering the value parameters above
logic [FIFO_MSB:FIFO_LSB] fifo;
logic [LOG2(DEPTH):0] depth;
always #(posedge clk or posedge reset) begin
casez ({read,write,reset})
// implementation of fifo
endcase
end
endmodule
Exactly. As per the Verilog IEEE Std 1364-2001, you can use localparam in your Verilog code. It can be declared after wire declaration, no problem for that.
Related
While implementing Verilog code in behavioral modeling we are using reg as output. But, when I have to use module instantiation and connect it using a wire, it's showing an error while implementation. Is there any other way where I can use module instantiation to connect outputs of different module instances to implement combinational logic as it's illegal to connect the reg output of the previous model to a wire? Note that I have to apply behavioral modeling hence no assignment statements are allowed. This is an example to connect two half adders to one full adder.
module half_adder(input wire a,b,output reg sum,output reg carry);
always#(a or b)
begin
sum = a^b ;
carry= a & b ;
end
endmodule
module full_adder(input wire a,b,c,output reg sum,output reg carry);
wire s1,c1,c2;
half_adder gate1(a,b,s1,c1);
half_adder gate2(s1,c,sum,c2);
always#(a or b or c)
begin
carry = c1|c2;
end
endmodule
Error (10663): Verilog HDL Port Connection error at full_adder.v(14):
output or inout port "sum" must be connected to a structural net
expression
In standard old verilog a reg cannot be connected to a reg using module connection or a continuous assignment. System verilog allows it. So, one of the solutions could be to switch to system verilog.
As for verilog, in half_adder port sum is declared as a reg. Instance gate2 connects variable of type reg to the port of type reg. This is illegal. This type of an assignment can only happen inside a procedural (i.e. always) block. Instance gate1 bypasses this issue by connecting port to the wire s1.
So, you can follow the similar path. Create another wire s2 as in the following example.
module full_adder(input wire a,b,c,output reg sum,output reg carry);
wire s1,c1, s2, c2;
half_adder gate1(a,b,s1,c1);
half_adder gate2(s1,c,s2,c2); // use s2 here
always#*
carry = c1|c2;
always #*
sum = s2; // now you can s2 assign to the 'sum' port
endmodule
Another way is to declare the 'sum' port as a wire. A register can be connected to a wire, using port connections or continuous assignment.
module full_adder(input wire a,b,c,
output sum, // declares it as a wire
output reg carry);
...
half_adder gate2(s1,c,sum,c2); // now it works this way.
And btw, do not use #(a,b,c). It is always error prone and is just wrong in your case. It should be #(c1,c2). But it is much better to use #*.
You should not declare sum as a reg in the full_adder module because it is not being assigned inside a procedural block (such as always). A reg is not a "net" type. Change:
module full_adder(input wire a,b,c,output reg sum,output reg carry);
to:
module full_adder(input wire a,b,c,output sum,output reg carry);
You also have an incorrect sensitivity list. Change:
always#(a or b or c)
to:
always #*
Now, the always block will trigger when the signals on the RHS of the assignments change.
I'm writing a code in Verilog which would count till 15 on every edge of a clock and would go back to 0. However, I'm not able to display waveforms. All I can see is Z (high impedance).
`timescale 1ns / 1ps
module Counter(
input ck,
output [3:0] a
);
reg a;
reg [3:0] i = 4'b0000;
always#(posedge ck)
begin
a = i;
if(i==15)
i = 0;
else
i = i+1;
end
endmodule
Here is the testbench to drive it:
module Counter_tb;
wire clock;
wire [3:0] ta;
Clocker mygate(.clk(clock));
Counter mygate2(.ck(clock), .a(ta));
initial
begin
$display(ta, clock);
end
endmodule
The waveform of clock is displayed properly, but not ta. What could be the possible mistake?
You declared a twice, once as an 4-bit output (inferred wire type), and once a an internal single bit reg. The way you did it is non-compliant with the IEEE standard because is does not follow the ANSI or non-ANSI style. Some simulators may allow what you did and work correctly, others throw compiling errors (strict IEEE compliance), and some get confused. I'm guessing the latter is what happened with your simulator; maybe there was a warning message in your compile log you over looked.
Get rid of the line reg a; and change output [3:0] a to output reg [3:0] a to make it compatible with an ANSI style header. With an ANSI portlist style, the ports direction, type, width, and name are declared on the same name.
module Counter(
input ck,
output reg [3:0] a
);
The Alternative is the Non-ANSI style (not recommended), which is required one line for declaring the port order, another for the direction & size, and a optional additional line to make it a reg. A proper Non-ANSI style header below.The Non-ANSI style header is required with IEEE1364-1995. ANSI was added and became the recommended styles since IEEE1364-2001, with non-ANSI supported so legacy code could continue being used.
module Counter(ck, a);
input ck;
output [3:0] a;
reg [3:0] a;
Other note, flops should be assigned with non-blocking (<=) assignments, instead of blocking (=) assignments. At minimum change a = i; to a <= i; to get in the practice of proper coding style that will avoid race conditions in the verilog scheduler.
You call "$display" once at time 0. What you are expecting to see?
Try to change $display to "$monitor(ta, clock);".
I'm trying to implement a simple verilog code as below:
module test1(
input ACLK,
input RST,
output test_output1,
output test_output2
);
//wire ACLK;
//wire RST;
reg test_output1;
reg test_output2;
assign test_output1 = ACLK;
always #(posedge ACLK or negedge RST)
begin
if(!RST)
begin
//test_output1 <=0;
test_output2 <=0;
end
else
begin
//test_output1 <=0;
test_output2 <=1;
end
end
endmodule
I get the following error message when I try to synthesize it in Xilinx ISE:
=========================================================================
* HDL Compilation *
=========================================================================
Compiling verilog file "test1.v" in library work
ERROR:HDLCompilers:27 - "test1.v" line 30 Illegal redeclaration of 'test_output1'
ERROR:HDLCompilers:27 - "test1.v" line 31 Illegal redeclaration of 'test_output2`
I am unable to resolve this error. Any help would be highly appreciated.
If you declare the directional of the port in the portlist, you must also declare the type. This is referred to as an ANSI style header.
There is also a non-ANSI style header that separates the portlist, directional, and type. If you are fallowing IEEE1364-1995 convention then you must use non-ANSI style and you cannot declare the type (e.g. output reg test_output2; is illegal, while output test_output2; reg test_output2; is legal). Since IEEE1364-2001 ANSI and non-ANSI style is supported (and the non-ANSI allows output reg test_output2;). All modern Verilog simulators are SystemVerilog (IEEE1800) simulators, therefore it is the designers choice. (ANSI style is more popular as it is less typing).
ANSI style header:
module test1(
input ACLK,
input RST,
output test_output1,
output reg test_output2 );
Non-ANSI style header:
module test1( ACLK, RST, test_output1, test_output2 );
input ACLK;
input RST;
output test_output1;
output test_output2;
reg test_output2;
Note: With IEEE1364, you can not drive a reg with an assign statement, it must be a net type. IEEE1800 has softened the rule the it is recommenced logic in stead of reg, but generally if you are going to use assign then you should be assigning a net (e.g. wire).
Add following modification:
You used test_output1 in assign statement so it should be of type wire.
module test1(
input wire ACLK,
input wire RST,
output wire test_output1,
output reg test_output2
);
You have already declared test_output1 and test_outpu2 as output and it is by default of type wire, so you just have to implicitly specify wire or reg according to usage,
// reg test_output1;
// reg test_output2;
I' trying to store value from wire named 'in' into reg 'a'.
But, the problem is value of reg 'a' is showing 'xxxx' in simulator. However, value of wire 'in' is showing correctly.
My target is just to read value from input wire and store it into a register.
module test(
input [3:0] in,
output [3:0] out
);
reg [3:0] a;
initial
begin
a = in;
end
endmodule
The reason why the value of a is 'xxxx' in the simulation is probably that a is set to the value of in only a single time initially, and a may not yet have been set to any specific value at this time in the simulation.
Declaring a reg in Verilog does not necessarily mean that a hardware register is described by the code. That usually involves the use of a clock signal:
module test(
input clk,
input [3:0] in,
output [3:0] out
);
// this describes a register with input "in" and output "a"
reg [3:0] a;
always #(posedge clk) begin
a <= in;
end
// I assume you want "a" to be the output of the module
assign out = a;
endmodule
Here is a counter example where a reg is used to describe something which is not a register, but only a simple wire:
module not_a_register(
input in,
output out
);
reg a;
always #(in) begin
a <= in;
end
assign out = a;
endmodule
Also note that I have used the non-blocking assignment operator <= inside the always block, which is good practice when describing synchronous logic. You can read more about it here.
Here i have a shifter but as of rite now it only works for up to 3 bits. I've been looking and i can't find out how to make it work for up to 8 bits.
module shifter(a,b,out);
input [7:0] a, b;
output [7:0] out;
wire [7:0] out1, out2, out3;
mux_8b_2to1 first(a[7:0], {a[3:0],a[7:4]}, b[2], out1);
mux_8b_2to1 second(out1[7:0], {out1[5:0],out1[7:6]}, b[1], out2);
mux_8b_2to1 third(out2[7:0], {out2[6:0],out2[7]}, b[0], out);
endmodule
What you have is a Barrel Shifter. Two ways to make it more generic are make it a functional model (still synthesis-able) or structural model with a generate block. Both approaches follow IEEE Std 1364-2001 (aka Verilog-2001).
The functional generic approach for a barrel shifter only needs a down-shifter. The general function is out = {in,in} >> (WIDTH-shift) where leftover bits can be ignored. To protect for double-roll (i.e. shift > WIDTH ), use the mod operator on the shift (WIDTH-(shift%WIDTH)).
module barrel_shifter_functional #( parameter CTRL=3, parameter WIDTH=CTRL**2 )
( input wire [WIDTH-1:0] in,
input wire [ CTRL-1:0] shift,
output wire [WIDTH-1:0] out );
assign out = {2{in}} >> (WIDTH-(shift%WIDTH));
endmodule
The structural generic approach for a barrel shifter needs a generate block. The for loop in the generate block will unravel at compile time, not run time like a for loop like in an always block. To keep it generic also have have the 2-to-1 mux have a parametrized width. FYI, you can use the generate block with functional code too, for example comment out the mux_2to1 instantiation and uncomment the assign statement below it. Learn more about the generate block by reading IEEE Std 1800-2012 ยง 27. Generate constructs.
module barrel_shifter_structeral #( parameter CTRL=3, parameter WIDTH=CTRL**2 )
( input wire [WIDTH-1:0] in,
input wire [ CTRL-1:0] shift,
output wire [WIDTH-1:0] out );
wire [WIDTH-1:0] tmp [CTRL:0];
assign tmp[CTRL] = in;
assign out = tmp[0];
genvar i;
generate
for (i = 0; i < CTRL; i = i + 1) begin : mux
mux_2to1 #(.WIDTH(WIDTH)) g(
.in0(tmp[i+1]),
.in1({tmp[i+1][WIDTH-(2**i)-1:0],tmp[i+1][WIDTH-1:WIDTH-(2**i)]}),
.sel(shift[i]),
.out(tmp[i]) );
// assign tmp[i] = shift[i] ? {tmp[i+1][WIDTH-(2**i)-1:0],tmp[i+1][WIDTH-1:WIDTH-(2**i)]} : tmp[i+1];
end : mux
endgenerate
endmodule
module mux_2to1 #( parameter WIDTH=8 )
( input wire [WIDTH-1:0] in0, in1,
input wire sel,
output wire [WIDTH-1:0] out );
assign out = sel ? in1 : in0;
endmodule
Both examples are functionally equivalent and synthesize provided CTRL is less than or equal to the ceiling of log2(WIDTH). Synthesis will likely give different results. The generate method will exclusively use 2-to-1 muxes while the pure functional method will depend on the quality of the optimizer.
Working example # http://www.edaplayground.com/s/6/500
I've used the >> and << operators to generate a synthetizable design using ISEWebPack, as this:
module shifter(
input wire [7:0] a,
input wire [7:0] b,
input wire leftright, // 0=shift right, 1=shift left
output reg [7:0] out
);
always #* begin
if (leftright==0)
out = a>>b;
else
out = a<<b;
end
endmodule
This way, the symthesis tool will know that you want to implement a shifter and can use its own macros to best synthetize it:
Synthesizing Unit <shifter>.
Related source file is "shifter.v".
Found 8-bit shifter logical right for signal <out$shift0002> created at line 30.
Found 8-bit shifter logical left for signal <out$shift0003> created at line 32.