I have written some Verilog code for an adder with 10 inputs. After simulation I am getting the output with one extra clock delay. Why am I getting this delay?
`timescale 1ns/1ps
module add_10(z0,z1,z2,z3,z4,z5,z6,z7,z8,z9,clk,reset,o);
input [7:0] z0,z1,z2,z3,z4,z5,z6,z7,z8,z9;
input clk,reset;
output reg[15:0] o;
always # (posedge clk or negedge reset)
begin
if (!reset)
o=16'b0000;
else
o = z0+z1+z2+z3+z4+z5+z6+z7+z8+z9;
end
endmodule
After asserting the reset, I am getting the output after one clock. But according to the code I wrote, it should come at the next posedge clk when reset=1.
It looks like it's working as it should to me.
I think you're misunderstanding how the reset signal is meant to be used. The reset signal should be kept high at all times. When it goes low, the output will be cleared immediately (it changes on the negative edge). When it goes high, the output will take on the sum of the inputs on the next clock cycle.
If you wanted to update on the positive edge of the reset signal, use the positive edge...
always # (posedge clk or posedge reset)
...
Just beware that doing so will likely affect your minimum cycle times.
I suggest you change the timing of reset with respect to clk in your testbench. The way you have it, reset and clk change simultaneously. I believe the simulator enters your always block as a result of posedge clk, while the value of reset is still 0, and therefore assigns 0 to your output.
I would shift the reset to the left or to the right of the posedge of the clock. That should give you the effect you are looking for.
Your code is probably working as expected, but it may not be. The issue is (a) that you're not showing how reset is generated, and (b) you're using blocking assignments (which you shouldn't be; use <=), so you may have a race elsewhere, in your reset generation.
Show the code that generates reset. If there are no race conditions, then your waveform is correct; edge A clears reset, but this isn't seen by your adder, which thinks that reset is still asserted; the adder sees it de-asserted on the next clock edge, so produces a result.
Related
I'm trying to add an edge_triggered reset to my module, meaning that only if a transient from 0 to 1 detected in reset, the reset operation should be perform.
and further more, I don't want to use any initial block in my module (because I think initial blocks have issues in FPGAs).
finally, I decided to following something like this:
always # (posedge clock, posedge reset) ...
but the problem I encountered, is that I need to know which element of always block sensitivity list is activated.
also I think this method isn't a proper solution:
always # (posedge clock, posedge reset) begin
if(reset) begin
//doing reset operations
end
.
.
.
end
because if reset is 1 from previous clocks (not transient from 0 to 1) in next posedge clock the reset operation will be perform! but we didn't want this.
so, is there any way to find out which element of sensitivity list activated the always block?
or even any other solution for implementing edge_triggered reset?
There almost certainly isn't a primitive in your FPGA that will do exactly what you want. And even in simulation, you wouldn't be able to tell which of the edges in the sensitivity list triggered the update.
The code you posted should synthesize, but as you noted it will behave like a standard asynchronous reset and continue to reset as long as reset is high. In order to reset only on the reset rising edge, you'll need some clock domain crossing logic to detect the edge and output a single pulse on the clock domain.
For example:
// This module can assert reset_pulse asynchronously but must output a pulse
// for at least one 'clock' cycle and deassert synchronously.
async_edge_to_pulse e2p (
.in_edge (reset),
.out_clock (clock),
.out_pulse (reset_pulse)
);
always #(posedge clock or posedge reset_pulse) begin
if (reset_pulse) begin
// reset logic
end else begin
// operational logic
end
end
I'm trying to implement a controller with the function that sends out the same clock signal as its input clock. But the controller can also halt the output signal if needed. I'm implementing it on Xilinx ISE.
My idea is: At the negedge of the input clock, the output clock signal set to 0. At the posedge of the input clock, if I want to send out the clock I'll set the output clock to 1, but if I want to halt the output clock, I'll set the output clock to 0 so other devices (all posedge-triggered) won't detect the posedge.
Here's my design:
module controller(
input clk_in,
input reset,
output clk_out
//and other ports
);
always #(negedge clk_in)
clk_out<=0;
always #(posedge clk_in)
if(reset)
clk_out<=1;
else
begin
case(cases)
case1:
begin
//do something and halt the output clock
clk_out<=0;
end
case2:
begin
//do something and continue the output clock
clk_out<=1;
end
endcase
end
When I synthesized the design I had an error saying the signal clk_out is connected to multiple drivers. Is there any way to solve it?
You have two different always blocks which drive the same signal clk_out. This is what synthesis tells you about. All signals in a synthesizable rtl must be driven from a single block only.
It looks like you are trying to create some type of a gated clock. Instead of going through the trouble of detecting negedges of the clock, which most likely will not be synthesizable as well, you can use a simple logic to do so:
always #*
clk_out = enable & clk_in;
You just have to figure out how to generate enable.
BTW, never use NBAs (<=) in generating clock signals or you end up with clock/data race conditions.
I am trying to make a module that performs the twos complement of a value if the msb is 1. It works in cadence, however when I try to synthesize it I get the following error:
Cannot test variable X_parallel because it was not in the event expression or with wrong polarity.
The code for the module is as follows:
module xTwosComp (X_parallel, Clk, Reset, X_pos);
input [13:0] X_parallel;
input Clk, Reset;
//wire X_msb; //was an attempt at fixing the problem
output [13:0] X_pos;
reg [13:0] X_pos;
//assign X_msb=X_parallel[13];//failled attempt at fixing
always # (posedge Clk or posedge Reset)
begin
if (X_parallel[13]) begin
X_pos = ~(X_parallel) +1;
end else begin
X_pos = X_parallel;
end
end
endmodule
You are missing your reset statement. Not sure if this fixes the exact error, but synthesizers expect code to determine what events are asynchronous when there is more than one edge event.
You need an if (Reset) begin X_pos <= 14'b0; else before the if (X_parallel[13]). Otherwise posedge Reset is treated as another clock and not a asynchronous reset. This will confuse the synthesizer.
FYI: flops should be assigned with non-blocking assignments (<=). It will save you from debugging false race condition and RTL to gates simulation mismatches.
After countless hours I have figured it out. It was because i was not referencing Clk or Reset in my always block.
Thanks to anyone who considered the issue.
Thanks Greg for your answer, although I figured out how to make it work I am very glad for your response since it cleared up why it works now. Thanks!
Let's take the example code below:
always #(posedge clock)
begin
if (reset == 1)
begin
something <= 0
end
end
Now let's say reset changes from 0 to 1 at the same time there's a posedge for the clock. Will something <= 0 at that point? Or will that happen the next time there's a posedge for the clock (assuming reset stays at 1)?
It depends on exactly how reset is driven.
If reset and something are both triggered off the same clock, then something will go to 0 one clock cycle after reset goes to 1. For example:
always #(posedge clock)
begin
if (somethingelse)
begin
reset <= 1;
end
end
If reset is synchronous and based on clock, The simulatore will defiantly see reset on the next clock and not the current. Physical design has clock-to-Q, therefor a rise in reset will not be observed in the same clock that caused it. You may see reset at the same time as clock in waveform. reset <= 1'b1; make the assignment happen near the end of the scheduler (after all code has executed).
To not have to worry about this when looking at a waveform, some logic designers like to put a delay on the assignment creating an artificial clock-to-Q delay (ex reset <= #1 1'b1; and something <=#1 0;). Synthesis tools will ignore the delay, but some will give warnings. That warning can be avoided by using a macro.
`ifdef SYNTHESIS
`define Q /* blank */
`else
`define Q #1
`endif
...
reset <= `Q 1'b1;
...
something <=`Q 1'b1;
...
If reset is asynchronous and being use with synchronous reset, setup time requirements need to be respected. In simulation if clock and reset rise at the same time, it is up to your verilog scheduler to decide if reset will be the new value or old value. Usually it will take the left-hand side value (old value), which means the reset will be missed on the current clock. Physical design uncertainly as well with a meta-stability risk.
The code you have written infers a flip-flop with synchronous reset. This means it is assumed that the "reset" signal is synchronised to the "clock" domain before being used in this way. If the "reset" signal is not synchronised then you should modify the code to infer a flip-flop with asynchronous reset as below:
always#(posedge clock or posedge reset)
begin
if (reset)
something <= 0
else
something <= something_else
end
Coming back to your question and assuming the code you have written is what you want, the outcome depends on how the reset is driven. If it is synchronous then the simulator will see it in the next clock edge. If it is asynchronous then the simulator can assume anything, it can vary from simulator to simulator. Please note that in simulator everything is a sequence of events and there is no such thing as happening at the same time.
In the physical world, what you have coded will result in a flip-flop with reset signal being one of the inputs to the combo driving the input of this flop. Now if the reset is synchronous, you are guaranteed that there will be no setup or hold violation at this flop. Whether the flop will 'see' the reset in this clock or the next depends on the various delays of the synthesised circuit (Usually this is the main reason that the reset is always held for few clock cycles to make sure all the flops in your design sees the reset). If reset is asynchronous then the flop will go into a metastable state. You will never want this in your design.
Hope this clarifies.
The short answer is that either of your two outcomes (immediately, or next cycle) could happen. This is a standard race condition, and simulators are free to handle this any way they want; some will give one answer, and others will give the other one.
For the long answer, look up any introductory text on how VHDL delta cycles work. Verilog doesn't specify 'delta cycles', but any Verilog simulator will work in exactly the same way, with some (irrelevant) changes in the overall scheduling algorithm. In this case, the scheduler finds that it has two events on the queue in a specific delta - reset rising, and clock rising. This is what "at the same time" means. It chooses one in an unspecified way (it might be earlier in the text source, or later, for example), works through all changes associated with that edge, and then goes back and works through all changes associated with the other edge.
i just want to know the difference between this two statement
always #(posedge CLK)
begin
state <= next_state;
end
AND:
always #(CLK)
begin
case(CLK)
1'b1:
state <= next_state;
1'b0:
state <= state;
end
Is there a difference between both ?
Thanks
Not quite. posedge detects these transitions (from the LRM):
Table 43—Detecting posedge and negedge
To 0 1 x z
From
0 No edge posedge posedge posedge
1 negedge No edge negedge negedge
x negedge posedge No edge No edge
z negedge posedge No edge No edge
So, 0->x is a posedge, for example. Your second example only detects cases where CLK ends up as 1, so misses 0->x and 0->z.
The IEEE Std. 1364.1(E):2002 (IEC 624142(E):2005), the Verilog register transfer level synthesis standard, states in Sec. 5.1 that an always block without any posedge/negedge events in the sensitivity list is combinational logic. I.e. the signals in the event list are ignored and the block is synthesized as if an implicit expression list (#(*), #*) was used. The following example is given in the standard ("Example 4" on page 14):
always # (in)
if (ena)
out = in;
else
out = 1’b1;
// Supported, but simulation mismatch might occur.
// To assure the simulation will match the synthesized logic, add ena
// to the event list so the event list reads: always # (in or ena)
(the comment is also copied from the standard document)
I.e. for a synthesis tool your second block is effectively:
always #*
begin
case(CLK)
1'b1:
state <= next_state;
1'b0:
state <= state;
end
which is just a multiplexer with CLK as select input, next_state as active-1 input and the output (state) fed back as active-0 input. A smart synthesis tool might detect that this is identical to a d-type latch with CLK as enable-input and create a d-type latch instead of a combinational loop. Note that the synthesis tool is not required to detect this latch because the code explicitly assigns state in all branches (compare Sec. 5.3. of the standard).
Either way this is different from the d-type flip-flop your first code example would synthesize to. This is one of many cases where Verilog-code has different meaning in simulation and synthesis. Therefore it is important to (1) write synthesizeable Verilog code in a way that avoids this cases and (2) always run post-synthesis simulations of your design (even if you are also using formal verification!) to make sure you have successfully avoided this pitfalls.
Functionally, those two circuits describe the same behavior in verilog, so I think there should be no difference.
However you should generally use the first style, as that is the one that is standard for writing synthesizable code, and most understandable by anyone else reading your code. The latter style, while describing the correct behavior, may confuse some synthesizers that don't expect to see clocks that are both sensitive to positive and negative edge.
The two blocks are VERY different.
The top one gives you a flip-flop while the bottom one gives you a latch with a multiplexer with the CLK as the select signal.
The critical difference between the two blocks is that the top one is a synchronous block i.e. the posedge clk part while the bottom one is asynchronous with the CLK level, not edge.
A verilog simulator could do left-hand sampling of CLK, effectively making the the case(CLK) version the same as a negedge CLK flop. Otherwise the simulator will treat it like a posedge CLK flop. It really depends how it is handled in the scheduler of specific simulator (or how a particular synthesizer will process it).
The most common codding styles all use the first condition. It is explicitly clear to the synthesizer and anyone reading the code that state is intended to be a flip-flop with a positive edge clocking trigger.
There is also a simulation performance differences. The posedge CLK performances 2 CPU operations every clock period, while the case(CLK) will perform 6 CPU operations every clock period. Granted in this example the differences is insignificance, but in large designs the poor coding used everywhere will add up to hours of simulation time wasted.