I'm trying to create a modules that simulates 4-bit multiplier without using multiplication (*) , need just to use Half and Full adders , so I succeeded to program the solution from some instance , this is the code :
module HA(sout,cout,a,b);
output sout,cout;
input a,b;
assign sout = a^b;
assign cout = (a&b);
endmodule
module FA(sout,cout,a,b,cin);
output sout,cout;
input a,b,cin;
assign sout =(a^b^cin);
assign cout = ((a&b)|(a&cin)|(b&cin));
endmodule
module multiply4bits(product,inp1,inp2,clock,reset,load);
output [7:0]product;
input [3:0]inp1;
input [3:0]inp2;
input clock;
input reset;
input load;
wire x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12,x13,x14,x15,x16,x17;
always # (posedge clock )
begin
if(reset == 1)
begin
// something to reset
end
else if (load == 1)
begin
product[0] = (inp1[0]&inp2[0]);
HA HA1(product[1],x1,(inp1[1]&inp2[0]),(inp1[0]&inp2[1]));
FA FA1(x2,x3,(inp1[1]&inp2[1]),(inp1[0]&inp2[2]),x1);
FA FA2(x4,x5,(inp1[1]&inp2[2]),(inp1[0]&inp2[3]),x3);
HA HA2(x6,x7,(inp1[1]&inp2[3]),x5);
HA HA3(product[2],x15,x2,(inp1[2]&inp2[0]));
FA FA5(x14,x16,x4,(inp1[2]&inp2[1]),x15);
FA FA4(x13,x17,x6,(inp1[2]&inp2[2]),x16);
FA FA3(x9,x8,x7,(inp1[2]&inp2[3]),x17);
HA HA4(product[3],x12,x14,(inp1[3]&inp2[0]));
FA FA8(product[4],x11,x13,(inp1[3]&inp2[1]),x12);
FA FA7(product[5],x10,x9,(inp1[3]&inp2[2]),x11);
FA FA6(product[6],product[7],x8,(inp1[3]&inp2[3]),x10);
end
end
endmodule
The problem is that I get a lot of errors from the lines inside the condition if(load == 1)
when I test the code.
here are the errors :
Line 34: Procedural assignment to a non-register product is not permitted, left-hand side should be reg/integer/time/genvar
Line 35: Instantiation is not allowed in sequential area except checker instantiation
Line 36: Instantiation is not allowed in sequential area except checker instantiation
Line 37: Instantiation is not allowed in sequential area except checker instantiation
.
.
Line 46: Instantiation is not allowed in sequential area except checker instantiation
If I remove the always # .. and write the code outside of it the code works perfectly !
but i must use the clock in order to get this code work just on load = 1 .
If anyone can help me I'll be very thankful .
You can also do this way:
module mul4(ans,aa,bb,clk,load,);
input [3:0]aa,bb;
input load,clk;
output [7:0]ans;
reg rst;
always #(posedge clk)
begin
if(load)
rst=0;
else
rst=1;
end
multiply4bits mm(ans,aa,bb,cl,rst);
endmodule
module multiply4bits(product,inp1,inp2,clock,reset);
output [7:0]product;
input [3:0]inp1;
input [3:0]inp2;
input clock;
input reset;
wire x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12,x13,x14,x15,x16,x17;
assign product[0]= (inp1[0]&inp2[0]);
HA HA1(product[1],x1,(inp1[1]&inp2[0]),(inp1[0]&inp2[1]));
FA FA1(x2,x3,(inp1[1]&inp2[1]),(inp1[0]&inp2[2]),x1);
FA FA2(x4,x5,(inp1[1]&inp2[2]),(inp1[0]&inp2[3]),x3);
HA HA2(x6,x7,(inp1[1]&inp2[3]),x5);
HA HA3(product[2],x15,x2,(inp1[2]&inp2[0]));
FA FA5(x14,x16,x4,(inp1[2]&inp2[1]),x15);
FA FA4(x13,x17,x6,(inp1[2]&inp2[2]),x16);
FA FA3(x9,x8,x7,(inp1[2]&inp2[3]),x17);
HA HA4(product[3],x12,x14,(inp1[3]&inp2[0]));
FA FA8(product[4],x11,x13,(inp1[3]&inp2[1]),x12);
FA FA7(product[5],x10,x9,(inp1[3]&inp2[2]),x11);
FA FA6(product[6],product[7],x8,(inp1[3]&inp2[3]),x10);
endmodule
module HA(sout,cout,a,b);
output sout,cout;
input a,b;
assign sout = a^b;
assign cout = (a&b);
endmodule
module FA(sout,cout,a,b,cin);
output sout,cout;
input a,b,cin;
assign sout =(a^b^cin);
assign cout = ((a&b)|(a&cin)|(b&cin));
endmodule
Hope it'll help.
Related
I am modelling a 4-bit register using D flip-flops with enable and asynchronous reset. It contains 4 D FF and 4 2:1 Mux. I used structural Verilog to model the circuit.
My design is shown below.
module DFlipFlop(D,clk,reset,Q);
input D;
input clk,reset;
output Q;
reg Q;
always #(posedge clk or posedge reset)
begin
if(reset==1'b1)
Q <= 1'b0;
else
Q <= D;
end
endmodule
module m21(D0, D1, S, Y);
output Y;
input D0, D1, S;
assign Y=(S)?D1:D0;
endmodule
module DFF_with_Enable(D,clk,enable,reset,Q);
input D,clk,reset,enable;
output Q;
reg Q;
wire in;
m21 mux(D,in,enable,in);
DFlipFlop DFF(in,clk,reset,Q);
endmodule
module fourbitreg(D,clk,reset,enable, Q);
input[0:3] D; // Data input
input clk,reset,enable;
output [3:0]Q;
reg [3:0]Q;
wire d0,d1,d2,d3;
wire q0,q1,q2,q3;
d0 = D[0];
d1 = D[1];
d2 = D[2];
d3 = D[3];
DFF_with_Enable df0(d0,clk,reset,enable,q0);
DFF_with_Enable df1(d1,clk,reset,enable,q1);
DFF_with_Enable df2(d2,clk,reset,enable,q2);
DFF_with_Enable df3(d3,clk,reset,enable,q3);
assign Q = {q0,q1,q2,q3};
endmodule
I used iverilog for simulation. How do I fix the following errors during compilation?
design.sv:37: syntax error
design.sv:37: error: Invalid module instantiation
design.sv:38: error: Invalid module instantiation
design.sv:39: error: Invalid module instantiation
design.sv:40: error: Invalid module instantiation
The circuit of 1 DFF MUX pair is shown below.
There are multiple compile errors.
Inside DFF_with_Enable and fourbitreg, do not declare Q as a reg because you make continuous assignments to Q.
You need to use the assign keyword to make continuous assignments to d0, etc.:
assign d0 = D[0];
assign d1 = D[1];
assign d2 = D[2];
assign d3 = D[3];
You should also try different simulators on edaplayground to get more meaningful error messages.
module mult(a, b, p);
input [16:0] a;
input [16:0] b;
output p;
wire [31:0] p;
reg i;
wire pv;
wire bp;
assign pv = 32'b0;
assign bp = {16'b0,b} ;
initial begin
for (i = 0; i < 32 ; i = i + 1)
begin
if (a[i] == 1'b1)
begin
pv <= pv + bp;
end
bp <= bp << 1 ;
end
end
assign p = pv;
endmodule
I get the following error while compiling the code,
line 37 Reference to scalar wire 'pv' is not a legal reg or variable lvalue
line 37 Illegal left hand side of nonblocking assignment
line 39 Reference to scalar wire 'bp' is not a legal reg or variable lvalue
line 39 Illegal left hand side of nonblocking assignment
Pls help.
Left hand side of assignment in always and initial blocks must be registers. pv and bp are wires instead of registers.
you cannot put a variable in left hand side of assign and always block at the same time. Because always needs registers and assign needs wires.
I see obvious semantic mistakes in your code . You need to study basics of Verilog. You put assign which means you expect a continuous assignment but an initial block is executed just once in the beginning of simulation.
By the way output is wire by default. you can declare it as output [31:0] p;
I am a newbie to xilinx so please excuse any stupidities in the code.
Ah so I am trying to design an 8-bit ALU and the module is working perfectly on the simulation but we need to take inputs and display outputs on FPGA board.
Technically I should have used RS-232 but since we just have an 8-bit input and 8 switches are available, we are trying to code it this way.
However, the code does not compile and gives error
"expecting 'endmodule', found 'forever'".
I used 'forever' and not 'always' because always does not allow any instance to be instantiated within it.
Can anybody please help us figure out what is wrong with the code?
module main(out,in,switch);
output [7:0] out;
input [7:0] in;
input switch;
reg [7:0] a,b,select;
reg [1:0] count;
wire eq, comp, C8;
initial
begin
count = 2'b00;
select = 8'b0000_0000;
end
MyALU A(eq, comp, C8, out, a, b, 1'b0, select[0], select[1], select[2], select[3]);
forever
begin
if (switch)
begin
case (count)
00:
begin
a = in;
count = 2'b01;
end
01:
begin
b = in;
count = 2'b10;
end
10:
begin
select = in;
A(eq, comp, C8, out, a, b, 1'b0, select[0], select[1], select[2], select[3]);
count = 2'b00;
end
default
a = in;
endcase
end
end
Every module in verilog must end with the line endmodule. That is missing in your code. And try using always#(*) instead of forever. forever is not synthesizable and only used for verification with simulation.
Replace the forever statement by always #(*).
Remove this line from the case statement:
A(eq, comp, C8, out, a, b, 1'b0, select[0], select[1], select[2], select[3]);
Add endmodule at the end.
I need to design a rightshift unit that have 4 module (logic,rotate,rotate with carry and arithmetic shift). I've written each module individual and they all work, but I need a multiplexer to recall each module in shift module.
module lshr(a,lout);
input [7:0]a;
output [7:0]out;
assign lout[7]=0;
assign lout[6:0]= a[7:1];
endmodule
module rshr(a,rout);
input [7:0]a;
output [7:0]rout;
assign rout[7]=a[0];
assign rout[6:0]= a[7:1];
endmodule
module rcshr(a,cin,rcout);
input [7:0]a;
input cin;
output [7:0]rcout;
assign rcout[7]=cin;
assign rcout[6:0]= a[7:1];
endmodule
module ashr(a,aout);
input [7:0]a;
output [7:0]aout;
assign aout[7]=a[7];
assign aout[6:0]=a[7:1];
endmodule
module mux418bit(a,b,c,d,s0,s1,e);
input[7:0]a,b,c,d;
input s0,s1;
output[7:0]e;
module sru(a,cin,s0,s1,out);
input[7:0]a;
input cin
input s0,s1;
output[7:0]out;
????? i dont know what to do here!
endmodule
What you need to do is use modules that you've created as submodules in sru module, i.e.:
module sru(a,cin,s0,s1,out);
input[7:0]a;
input cin;
input s0,s1;
output [7:0]out;
wire [7:0] lshr_out, rshr_out, rcshr_out, ashr_out;
lshr m1(a, lshr_out);
rshr m2(a, rshr_out);
rcshr m3(a, cin, rcshr_out);
ashr m4(a, ashr_out);
mux418bit m5(lshr_out, rshr_out, rcshr_out, ashr_out, s0, s1, out);
endmodule
As you can see, your four modules (lshr, rshr, rcshr, ashr) were declared as submodules inside sru (m1,...,m5). The output from these modules is multiplexed (inside m5 submodule) depending on s0 and s1 values (case construct is responsible for that).
You can check that this code compiles without any errors here.
One other thing, your mux418bit module is not finished. Probably you want to achieve something like this:
module mux418bit(a,b,c,d,s0,s1,e);
input[7:0]a,b,c,d;
input s0,s1;
output reg [7:0]e;
always #(*) begin
case({s0,s1})
2'b00 : e = a;
2'b01 : e = b;
2'b10 : e = c;
2'b11 : e = d;
endcase
end
endmodule
In situation when you can't use case construct:
module mux418bit(a,b,c,d,s0,s1,e);
input[7:0]a,b,c,d;
input s0,s1;
output [7:0]e;
assign e = ({s0,s1} == 2'b00) ? a :
({s0,s1} == 2'b01) ? b :
({s0,s1} == 2'b10) ? c : d;
endmodule
I am trying to debug my code shown below. I am fairly new to SystemVerilog and hopefully I can learn from this. Let me know of any suggestions.
**The errors I am receiving are:
Error-[ICPSD] Invalid combination of drivers
Variable "Q" is driven by an invalid combination of structural and
procedural drivers. Variables driven by a structural driver cannot have any
other drivers.
"divide.v", 13: logic [7:0] Q;
"divide.v", 16: divide8bit testcase1(x, y, clk, Q, R);
"divide.v", 23: Q = 8'b0;
Error-[ICPSD] Invalid combination of drivers
Variable "R" is driven by an invalid combination of structural and
procedural drivers. Variables driven by a structural driver cannot have any
other drivers.
"divide.v", 13: logic [7:0] R;
"divide.v", 16: divide8bit testcase1(x, y, clk, Q, R);
"divide.v", 24: R = y;
**My SystemVerilog Code is:
module divide8bit(
input logic [7:0] x,y,
input logic clk,
output logic [7:0] Q,R);
always_ff #(posedge clk)
begin
R <= R-x;
Q <= Q + 8'd1;
end
endmodule
module test1;
logic [7:0] x,y,Q,R;
logic clk;
divide8bit testcase1 (x,y,clk,Q,R);
initial
begin
x = 8'd2;
y = 8'd8;
Q = 8'd0;
R = y;
clk = 1'd0;
while(x <= R)
begin
#5 clk = ~clk;
end
#5 $finish;
end
endmodule
Same problem here: you are assigning to Q and R inside module test1. At the same time module testcase1 is also trying to assing to Q and R. Don't assign to Q and R in test1!