I use kernel 3.12.rc4 on an embedded linux device (olimex imx233 micro). My aim is to use /dev/spidev to be able to communicate with another spi device.
I edit arch/arm/boot/dts/imx23-olinuxino.dts as:
ssp1: ssp#80034000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx23-spi";
pinctrl-names = "default";
pinctrl-0 = <&spi2_pins_a>;
clock-frequency = <1000000>;
status = "okay";
spidev: spidev#0 {
compatible = "spidev";
spi-max-frequency = <1000000>;
reg = <1>;
};
};
arch/arm/boot/dts/imx23.dtsi: has this config
spi2_pins_a: spi2#0 {
reg = <0>;
fsl,pinmux-ids = <
0x0182 /* MX23_PAD_GPMI_WRN__SSP2_SCK */
0x0142 /* MX23_PAD_GPMI_RDY1__SSP2_CMD */
0x0002 /* MX23_PAD_GPMI_D00__SSP2_DATA0 */
0x0032 /* MX23_PAD_GPMI_D03__SSP2_DATA3 */
>;
fsl,drive-strength = <1>;
fsl,voltage = <1>;
fsl,pull-up = <1>;
};
Device binding looks correct. When I compile the kernel I get the /dev/spidev1.1. After that I use spidev_test.c and monitor the pins by an oscilloscope. The SCK and MOSI output signals correctly, however, the chipselect is set to the logic high even during the data transfer.
Is there any way to determine why spidev cannot set to logic low during the transmission? It seems like either additional things needs to be passed on kernel or there is an issue on spidev that cannot control the chip select . I wonder if I need to change anything on the spidev.h or spidev.c on the driver/spi directory of the kernel? or how can I solve it?
The reference manual for the processor
I never used device tree, but I try to help you anyway.
The kernel create the device /dev/spidev1.1, so spidev is connected to SPI bus 1, chip select 1. The chip select numeration start from 0, and you do not have any other device associated to SPI bus 1.
As far as I know reg = <1> tell to the SPI core that spidev is connected to chip select 1., but maybe your device is connected to the chip select 0. So, reg = <0>
Related
I'm building a project using petalinux2020.2 and an RFSOC, zcu111 board, for my application I need to reserve a section of memory from petalinux to use with DMA, implemented on the programmable logic of the FPGA.
I tried following this tutorial, but I get an error at boot time.
Which terminates with a kernel panic, shown here:
I've tried to modify Memory Size by using petalinux-config command, setting the Memory Size to 0x70000000 but it did not help.
The entry for the device tree is shown here:
/include/ "system-conf.dtsi"
/{
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
reserved: buffer#0 {
no-map;
reg = <0x0 0x70000000 0x0 0x10000000>;
};
};
reserved-driver#0 {
compatible = "xlnx,reserved-memory";
memory-region = <&reserved>;
};
};
How can I make this work?
I'm running PetaLinux 2018.1 on a Zynq-7020 board and can successfully reserve memory for my DMA operations. While not your exact set up it should be similar enough. You'll need to adjust the memory addresses to suit your system.
I'm using the DMA API "shared-dma-pool" property. That way my device driver will use my reserved space instead of the default CMA pool.
Also, note that I had problems reserving the memory until I added the vmalloc=512M statement to the bootargs. Although I was only reserving 256MB for DMA, I needed to vmalloc a larger value (double in my case) to get things to work.
My device tree entry:
/include/ "system-conf.dtsi"
/ {
chosen {
bootargs = "console=ttyPS0,115200 earlyprintk vmalloc=512M";
stdout-path = "serial0:115200n8";
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
dma_reserved: buffer#30000000 {
compatible = "shared-dma-pool";
no-map;
reg = <0x30000000 0x10000000>;
};
};
//Required properties:
// - dmas: a list of <[DMA device phandle] [Channel ID]> pairs,
// where Channel ID is (if both channels are enabled):
// '0' for write/tx channel
// '1' for read/rx channel
// If only one channel is enabled, either tx or rx:
// Channel ID is '0'.
// - dma-names: a list of DMA channel names, one per "dmas" entry
dma_proxy#0 {
compatible ="xlnx,dma_proxy";
dmas = <&axi_dma_0 0;
dma-names = "dma1";
memory-region = <&dma_reserved>;
};
}
Console showing reserved memory (PetaLinux 2018.1):
Update:
I've since updated my design to a ZynqMP architecture using PetaLinux 2022.1 and wanted to post the differences I encountered while getting the reserved memory working.
I am booting with an initramfs image and also ran into trouble when trying to reserve memory in the 0x70000000 address space you see in the Xilinx Wiki. This is because the system likes to load the ramdisk into this region, so it's already booked when you try to reserve it, similar to what the OP ran into. Reserving a different address space (0x40000000 in the example below) is all it took to get it working.
/include/ "system-conf.dtsi"
/ {
chosen {
bootargs = "earlycon console=ttyPS0,115200 clk_ignore_unused";
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
dma_reserved: buffer#0 {
compatible = "shared-dma-pool";
no-map;
reg = <0x0 0x40000000 0x0 0x10000000>;
};
};
dma_proxy#0 {
compatible ="xlnx,dma_proxy";
dmas = <&axi_dma_0 1>;
dma-names = "dma1";
memory-region = <&dma_reserved>;
};
}
Console showing reserved memory (PetaLinux 2022.1):
I have a GPIO peripheral, defined in Device Tree as that:
gpio0: gpio#2300000
{
compatible = "fsl,qoriq-gpio";
reg = <0x0 0x2300000 0x0 0x10000>;
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
I want to write an interrupt handler for this (as a kernel module). But this IRQ number (66) is a hardware one and I need a virtual, Linux IRQ number to pass it to request_irq.
How can I get this number? There is only one interrupt controller (GIC).
Is there a way to do this without writing a platform device driver (as there is probably already one working in the system and I think I cannot register another one).
As per you comment you want to register a GPIO as an interrupt.
The node of device tree that you have posted is the interrupt controller node, which wont concern us for the task we have at hand.
To register a gpio as an interrupt, you first need to find a GPIO which can be configured as an interrupt (in most modern processors all GPIOs support it) and then you have to make sure it is not used by some other device by multiplexing it (if it is used by some one like SPI or UART etc , you can disable them from device tree if you are not using that entity).
now that you have a GPIO pin that you can use. Find the GPIO number on kernel that pin corresponds to (it depends on the architecture of your processor and its carrier board).
When you have that you can just write a simple module that will export your GPIO and use it as interrupt.
Below is a snippet from http://derekmolloy.ie
gpio_request(gpioButton, "sysfs"); // Set up the gpioButton
gpio_direction_input(gpioButton); // Set the button GPIO to be an input
gpio_set_debounce(gpioButton, 200); // Debounce the button with a delay of 200ms
gpio_export(gpioButton, false); // Causes gpio115 to appear in /sys/class/gpio
// the bool argument prevents the direction from being changed
// Perform a quick test to see that the button is working as expected on LKM load
printk(KERN_INFO "GPIO_TEST: The button state is currently: %d\n", gpio_get_value(gpioButton));
// GPIO numbers and IRQ numbers are not the same! This function performs the mapping for us
irqNumber = gpio_to_irq(gpioButton);
printk(KERN_INFO "GPIO_TEST: The button is mapped to IRQ: %d\n", irqNumber);
// This next call requests an interrupt line
result = request_irq(irqNumber, // The interrupt number requested
(irq_handler_t) ebbgpio_irq_handler, // The pointer to the handler function below
IRQF_TRIGGER_RISING, // Interrupt on rising edge (button press, not release)
"ebb_gpio_handler", // Used in /proc/interrupts to identify the owner
NULL); // The *dev_id for shared interrupt lines, NULL is okay
Link to the complete code.
For whom is not trying to create a GPIO driver but still need to get Linux virtual IRQ from HW IRQ, there is a specific API for platform drivers. You can register a platform driver and then, during the probing, call
/**
* platform_get_irq - get an IRQ for a device
* #dev: platform device
* #num: IRQ number index
*
* Gets an IRQ for a platform device and prints an error message if finding the
* IRQ fails. Device drivers should check the return value for errors so as to
* not pass a negative integer value to the request_irq() APIs.
*
* Return: non-zero IRQ number on success, negative error number on failure.
*/
int platform_get_irq(struct platform_device *dev, unsigned int num);
Detailed explanation
To reach your goal, you have a lot of different options:
GPIO Driver Interface (GPIO drivers providing IRQs)
Low-level OF API for Device Trees (of_irq_get)
Device drivers' infrastructure API (platform_get_irq)
GPIO Driver Interface
If your platform has a programmable GPIO, you can use the GPIO Driver Interface. See #yashC reply. In your specific case, given that your device is part of GPIO, you should go for this approach.
Low-level Device Trees APIs
If you want to interact directly with the device tree, you can use this solution. Imho, you should follow this approach only if you are writing a specific (and non-generic) driver and you need a "dirty and clean" way to go.
static const struct of_device_id qoriq_gpio_match_table[] =
{
{ .compatible = "fsl,qoriq-gpio" },
{ }
};
np = of_find_matching_node(NULL, qoriq_gpio_match_table);
if (!np)
{
pr_err("No device tree node for qoriq-gpio\n");
return -ENODEV;
}
// decode a node's IRQ and return it as a Linux IRQ number
irq_num = of_irq_get(np, 0);
// request_irq(...)
Device drivers' infrastructure API
Basically, you have to register a platform driver.
static const struct of_device_id qoriq_gpio_match_table[] =
{
{ .compatible = "fsl,qoriq-gpio" },
{ }
};
static struct platform_driver qoriq_gpi_driver = {
.driver = {
.name = "qoriq-gpio",
.of_match_table = qoriq_gpio_match_table
},
.probe = qoriq_gpio_probe
};
static int qoriq_gpio_probe(struct platform_device *pdev)
{
irq = platform_get_irq(pdev, 0);
if (irq < 0)
return irq;
// request_irq(...)
}
Until Kernel v5.19 you were able to use also: platform_get_resource(pdev, IORESOURCE_IRQ, 0); API that, currently, is no more available.
You should use this approach if your device is a bit more generic (eg. you are working with several boards with different DTs).
I have an Intel Galileo board with LED connected to one of GPIO pin. When I am connecting power to Galileo, LED lights up for a second and then turns off again.
Once my application start I am able to manipulate LED. But now I want my LED to turned ON during whole boot process and once my application starts it should manipulate LED after then. I guess to achieve this I have to change kernel code and build it again completely.
If possible, you can make the default state of the GPIO high/low in Boot loader. Or, Refer the following Changes in linux kernel and device tree.
:arch/xxx/boot/dts/xxxx.dts
led#4 {
label = "evmsk:green:heartbeat";
gpios = <&gpio1 7 0>;
linux,default-trigger = "heartbeat";
default-state = "off";
};
:drivers/leds/leds-gpio.c
state = of_get_property(child, "default-state", NULL);
if (state) {
if (!strcmp(state, "keep"))
led.default_state = LEDS_GPIO_DEFSTATE_KEEP;
else if (!strcmp(state, "on"))
led.default_state = LEDS_GPIO_DEFSTATE_ON;
else
led.default_state = LEDS_GPIO_DEFSTATE_OFF;
}
ret = gpio_direction_output(led_dat->gpio, led_dat->active_low ^ state);
I have an embedded system on which I can connect two different touch screen controllers (ft5x06 or sitronix) depending on my provider.
I would like to have only one software.
I put the two controllers in the device tree, and the probe mechanism will do the job!
i2c1: i2c#f0018000 {
edt-ft5x06#38 {
compatible = "edt,edt-ft5x06";
reg = <0x38>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ft5x06>;
interrupt-parent = <&pioE>;
interrupts = <7 0>;
reset-gpios = <&pioE 6 GPIO_ACTIVE_LOW>;
};
sitronix_ts#55 {
compatible = "sitronix,ST1633";
reg = <0x55>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_st1633>;
interrupt-parent = <&pioE>;
interrupts = <7 0>;
reset-gpios = <&pioE 6 GPIO_ACTIVE_LOW>;
};
};
It works except for the interrupt:
the ft5x06 get the IRQ 7 assigned, but the sitronix doesn't get it :(
(the probe function does not request the irq if the component is not detected on I2C bus, so the IRQ keep free for the other one).
Is there something to share this interrupt, or should I do it otherway?
I found this snippet in the dts file of a embedded product.
Why do we have a NOR flash when we have a NAND flash?
And what is the meaning of LCS0,LCS1 which is mentioned in the localbus node below?
localbus#a8405000 {
#address-cells = <2>;
#size-cells = <1>;
compatible = "fsl,mpc8313-elbc", "fsl,elbc", "simple-bus";
reg = <0xa8405000 0x1000>;
interrupts = <77 0x8>;
interrupt-parent = <&ipic>;
// CS0 and CS1 are swapped when
// booting from nand, but the
// addresses are the same.
// ranges = <0x0 0x0 0xfe000000 0x01000000 /* LCS0: NOR BOOT */
ranges = <0x0 0x0 0xfe000000 0x02000000 /* LCS0: NOR BOOT */
0x1 0x0 0xa8000000 0x00040000 /* LCS1: NAND CONTROLLER */
// 0x2 0x0 0xa0000000 0x04000000 /* LCS2: FGPA */
0x2 0x0 0xa0000000 0x04000000>; /* LCS2: FGPA */
// 0x3 0x0 0xff000000 0x01000000>; /* LCS3: NOR RESERVE */
flash#0,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "cfi-flash";
// reg = <0x0 0x0 0x1000000>; /* 16MB */
reg = <0x0 0x0 0x2000000>; /* 32MB */
bank-width = <2>;
device-width = <1>;
u-boot#0 {
reg = <0x0 0x80000>;
};
xxxx#80000 {
reg = <0x080000 0x1000000>;
};
log#1080000 {
reg = <0x1080000 0x2c0000>;
};
inventry#1340000 {
reg = <0x1340000 0x20000>;
};
xxxxx#1360000 {
reg = <0x1360000 0x20000>;
};
xxxxx#1380000 {
reg = <0x1380000 0x20000>;
};
xxxxx#13a0000 {
reg = <0x13a0000 0x20000>;
};
reserve-nor1#13c0000 {
reg = <0x13c0000 0xc40000>;
};
dummy1#2000000 {
reg = <0x2000000 0x0>;
};
dummy2#2000000 {
reg = <0x2000000 0x0>;
};
};
nand#1,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc8313-fcm-nand",
"fsl,elbc-fcm-nand";
reg = <0x1 0x0 0x40000>; /* NAND CONTROLLER 256KB */
dtb-0#0 {
reg = <0x0 0x20000>;
};
kernel-0#20000 {
reg = <0x20000 0x400000>;
};
rootfs-0#420000 {
reg = <0x420000 0x099e0000>;
};
dtb-1#9e00000 {
reg = <0x09e00000 0x20000>;
};
kernel-1#9e20000 {
reg = <0x09e20000 0x400000>;
};
rootfs-1#a220000 {
reg = <0x0a220000 0x099e0000>;
};
internal#13c00000 {
reg = <0x13c00000 0x6400000>;
};
xxxx-log#1a000000 {
reg = <0x1a000000 0x6000000>;
};
};
};
I completely do not get what the below snippet means
// CS0 and CS1 are swapped when
// booting from nand, but the
// addresses are the same.
// ranges = <0x0 0x0 0xfe000000 0x01000000 /* LCS0: NOR BOOT */
ranges = <0x0 0x0 0xfe000000 0x02000000 /* LCS0: NOR BOOT */
0x1 0x0 0xa8000000 0x00040000 /* LCS1: NAND CONTROLLER */
// 0x2 0x0 0xa0000000 0x04000000 /* LCS2: FGPA */
0x2 0x0 0xa0000000 0x04000000>; /* LCS2: FGPA */
// 0x3 0x0 0xff000000 0x01000000>; /* LCS3: NOR RESERVE */
NOR-flash is slower in erase-operation and write-operation compared to NAND-flash. That means the NAND-flash has faster erase and write times. More over NAND has smaller erase units. So fewer erases are needed. NOR-flash can read data slightly faster than NAND.
NOR offers complete address and data buses to randomly access any of its memory location (addressable to every byte). This makes it a suitable replacement for older ROM BIOS/firmware chips, which rarely needs to be updated. Its endurance is 10,000 to 1,000,000 erase cycles. NOR is highly suitable for storing code in embedded systems. Also the support for XiP(eXecute in Place) makes it a very attractive choice to load the initial boot-loader from (even before initialising DDR).
NAND-flash occupies smaller chip area per cell. This maker NAND available in greater storage densities and at lower costs per bit than NOR-flash. It also has up to ten times the endurance of NOR-flash. NAND is more fit as storage media for large files including video and audio. The USB thumb drives, SD cards and MMC cards are of NAND type.
NAND-flash does not provide a random-access external address bus so the data must be read on a block-wise basis (also known as page access), where each block holds hundreds to thousands of bits, resembling to a kind of sequential data access. This is one of the main reasons why the NAND-flash is unsuitable to replace the ROM, because most of the microprocessors and microcontrollers require byte-level random access.
Checkout Table 1 in this document illustrating the comparative merits of each.
LCSx refers to "Local Chip Select x". These are signals on a bus that when set will cause a chip to respond to data requests on that bus. So by setting LCS0 on flash chip will respond to CPU data requests and by setting LCS1 another chip will respond (or something like that). Think of them as an extra address bits.
NOR flash tends to get used for BIOS and bootroms because it is usually "error free", whereas use of NAND may require a software layer to provide error correction (which you wont have until a bootrom has loaded...).
It looks like you can choose to boot from NAND or NOR by swapping over a couple of chip select lines. That way when the CPU puts its boot address on the address lines of the bus you control which chip responds, the NOR or the NAND.