I am new in VHDL language so maybe it is dumb question but I didnt find any reference of this problem.
So, I am working on bit converter which convert specific combinations of 5 bits into other combinations. Problem is with case statement, where I dont know how to put five bits into one contition.
entity CONV is
port (ia, ib, ic, id, ie:in Bit; oa, ob, oc, od, oe:out Bit);
end CONV;
architecture BEH of CONV is
signal t: bit;
begin
case ia & ib & ic & id & ie is
when "00010" => t <= "00011";
when "00101" => t <= "00101";
when "01000" => t <= "00110";
when "01011" => t <= "01001";
when "01110" => t <= "01010";
when "10001" => t <= "01100";
when "10100" => t <= "10001";
when "10111" => t <= "10010";
when "11010" => t <= "10100";
when "11101" => t <= "11000";
when others => t <= "00000";
end case;
t => oa & ob & oc & od & oe;
end beh;
entity CONV is
port (
ia, ib, ic, id, ie: in Bit;
oa, ob, oc, od, oe: out Bit
);
end CONV;
architecture BEH of CONV is
signal t: bit_vector(0 to 4);
subtype fivebit is bit_vector(0 to 4);
begin
EVALUATE:
process (ia, ib, ic, id, ie)
begin
case fivebit(ia & ib & ic & id & ie) is
when "00010" => t <= "00011";
when "00101" => t <= "00101";
when "01000" => t <= "00110";
when "01011" => t <= "01001";
when "01110" => t <= "01010";
when "10001" => t <= "01100";
when "10100" => t <= "10001";
when "10111" => t <= "10010";
when "11010" => t <= "10100";
when "11101" => t <= "11000";
when others => t <= "00000";
end case;
end process;
OUTPUT:
(oa , ob , oc , od , oe) <= t;
end architecture BEH;
The expression being evaluated in a case statement must be one of: the name of an object with a locally static subtype (Russell's vector_in), an index name with locally static indexes, a slice name with a locally static range, a function call that returns a locally static subtype, or a qualified expression or type conversion with a locally static type mark (shown).
The idea being that analyzer (locally static means analysis time) can determine the number of elements in the expression and their type to determine case coverage.
The aggregate target for the concurrent signal assignment associates elements of the aggregate (oa , ob , oc , od , oe) with elements (Bits) of t on the right hand side individually. Each element association can occur only once.
The case statement is contained in a process (a concurrent statement) because it is a sequential statement. And to prevent any confusion there are both sequential and concurrent signal assignment statements. VHDL uses concurrent statements to provide parallelism.
With a test bench:
entity conv_test is
end entity;
architecture test of conv_test is
signal ia, ib, ic, id, ie: bit;
signal oa, ob, oc, od, oe: bit;
signal t: bit_vector (0 to 4);
signal input: bit_vector (0 to 4);
begin
DUT:
entity work.CONV
port map (
ia => ia, ib => ib, ic => ic, id => id, ie => ie,
oa => oa, ob => ob, oc => oc, od => od, oe => oe
)
;
TEST:
process
begin
wait for 10 ns; -- bit defaults to '0', others case
(ia, ib, ic, id, ie) <= bit_vector'("00010"); -- first case
wait for 10 ns;
(ia, ib, ic, id, ie) <= bit_vector'("00101");
wait for 10 ns;
(ia, ib, ic, id, ie) <= bit_vector'("01000");
wait for 10 ns;
(ia, ib, ic, id, ie) <= bit_vector'("01011");
wait for 10 ns;
(ia, ib, ic, id, ie) <= bit_vector'("01110");
wait for 10 ns;
(ia, ib, ic, id, ie) <= bit_vector'("10001");
wait for 10 ns;
(ia, ib, ic, id, ie) <= bit_vector'("10100");
wait for 10 ns;
(ia, ib, ic, id, ie) <= bit_vector'("10111");
wait for 10 ns;
(ia, ib, ic, id, ie) <= bit_vector'("11010");
wait for 10 ns;
(ia, ib, ic, id, ie) <= bit_vector'("11101");
wait for 10 ns;
(ia, ib, ic, id, ie) <= bit_vector'("11111"); -- others case
wait for 10 ns;
wait; -- one time only
end process;
SIM_INPUT:
input <= (ia & ib & ic & id & ie); -- for ease of viewing in waveform display
RESULT:
t <= (oa & ob & oc & od & oe);
end architecture;
You can test conv:
Note that the TEST process could be re-written much simpler assigning to input instead of the aggregate (ia, ib, ic, id, ie), by using
(ia , ib , ic , id , ie) <= input;
in the SIM_INPUT statement:
TEST:
process
begin
wait for 10 ns; -- bit defaults to '0', others case
input <= "00010"; -- first case
wait for 10 ns;
input <= "00101";
wait for 10 ns;
input <= "01000";
wait for 10 ns;
input <= "01011";
wait for 10 ns;
input <= "01110";
wait for 10 ns;
input <= "10001";
wait for 10 ns;
input <= "10100";
wait for 10 ns;
input <= "10111";
wait for 10 ns;
input <= "11010";
wait for 10 ns;
input <= "11101";
wait for 10 ns;
input <= "11111"; -- others case
wait for 10 ns;
wait; -- one time only
end process;
SIM_INPUT:
(ia, ib, ic, id, ie) <= input; -- for ease of viewing in waveform display
And get the same waveform display
Try this:
architecture BEH of CONV is
signal vector_in : bit_vector(4 downto 0);
signal vector_out : bit_vector(4 downto 0);
begin
case vector_in is
when "00010" => vector_out <= "00011";
when "00101" => vector_out <= "00101";
when "01000" => vector_out <= "00110";
when "01011" => vector_out <= "01001";
when "01110" => vector_out <= "01010";
when "10001" => vector_out <= "01100";
when "10100" => vector_out <= "10001";
when "10111" => vector_out <= "10010";
when "11010" => vector_out <= "10100";
when "11101" => vector_out <= "11000";
when others => vector_out <= "00000";
end case;
vector_in <= (ia & ib & ic & id & ie);
oa <= vector_out(4);
ob <= vector_out(3);
oc <= vector_out(2);
od <= vector_out(1);
oe <= vector_out(0);
Make sense?
You can put all the inputs into a bit vector like #Russell says. Then each bit in the bit vector represents an input. This makes things much easier.
And case statements are sequential statements(i.e. They must be put into a process or a procedure or a function).
entity CONV is
port (inp : in Bit_Vector(4 downto 0); -- [ai, bi, ci, di, ei]
outp: out Bit_Vector(4 downto 0)); -- [ao, bo, co, do, eo]
end CONV;
architecture BEH of CONV is
begin
process (inp)
begin
case inp is
when "00010" => outp <= "00011";
when "00101" => outp <= "00101";
when "01000" => outp <= "00110";
when "01011" => outp <= "01001";
when "01110" => outp <= "01010";
when "10001" => outp <= "01100";
when "10100" => outp <= "10001";
when "10111" => outp <= "10010";
when "11010" => outp <= "10100";
when "11101" => outp <= "11000";
when others => outp <= "00000";
end case;
end process;
end beh;
If you really want to use single bits for readablity or other reasons, just concatenate and interrupt them outside the process.
For pin planning, all you need is connect ai to inp[4], bi to inp[3] and so on.
Related
I want to write a Serial to Parallel conversion in Verilog, and I can't realize what is wrong with my code. It doesn't synthesize, and not even the ISE shows what the problem is. Can anyone help me?
I guess the problem is around the second always block. The part:
if (STATE == TRANSMIT)
PAR_OUT[COUNTER] = SER_IN;
seems wrong to me, but I can't understand what to change or test.
module SIPO(
input SER_IN,
input RST,
input CLK,
input LOAD,
output reg READY,
output reg [7:0] PAR_OUT
);
parameter IDLE = 2'b00, START = 2'b01, TRANSMIT = 2'b10, STOP = 2'b11;
reg [1:0] STATE;
reg [2:0] COUNTER;
always # ( posedge CLK or negedge RST)
if (~RST)
begin
STATE <= IDLE;
READY <= 1;
COUNTER <= 0;
end
else
begin
if (STATE == IDLE)
begin
READY <= 1;
COUNTER <= 0;
if (LOAD)
begin
STATE <= START;
end
else
STATE <= IDLE;
end
else
if (STATE == START)
STATE <= TRANSMIT;
else
if (STATE == TRANSMIT)
begin
COUNTER <= COUNTER + 1;
if (COUNTER == 7)
STATE <= STOP;
end
else
begin
STATE <= IDLE;
READY <= 1;
end
end
always #( * )
begin
if (STATE == IDLE)
PAR_OUT = 1;
else
if (STATE == START)
PAR_OUT = 0;
else
if (STATE == TRANSMIT)
PAR_OUT[COUNTER] = SER_IN;
else
PAR_OUT = 1;
end
endmodule
I think your suspicion might be correct regarding PAR_OUT[COUNTER]. When I synthesize your code on edaplayground with Yosys, it infers latches for PAR_OUT, which you likely do not want.
PAR_OUT is 8 bits wide, but you only assign 1 of the 8 bits at a time in the TRANSMIT state, which means the other 7 bits retain their state. For example, if COUNTER=3, then only PAR_OUT[3] is assigned.
I recoded your combo logic, simplifying it with a case statement to make the issue more evident (it should be functionally equivalent to your if/else code):
always #* begin
case (STATE)
TRANSMIT: PAR_OUT[COUNTER] = SER_IN; // Assign to only 1 bit <---
START : PAR_OUT = 8'h00; // Assign to all 8 bits
default : PAR_OUT = 8'h01; // Assign to all 8 bits
endcase
end
If you can afford one cycle of latency, you could use sequential logic for PAR_OUT, such as a shift register.
I have a very simple synchronous circuit that is supposed to blink an LED:
module Blinker where
import Clash.Prelude
import Data.Word
{-# NOINLINE topEntity #-}
{-# ANN topEntity
(Synthesize
{ t_name = "blinkerTop"
, t_inputs = [PortName "CLK_32MHZ", PortName "RESET"]
, t_output = PortName "LED"
}) #-}
topEntity
:: Clock System Source
-> Reset System Asynchronous
-> Signal System Bit
topEntity = exposeClockReset $ tickTock 32000000
tickTock :: (HiddenClockReset domain gated synchronous) => Word32 -> Signal domain Bit
tickTock n = mealy step (False, 0) (pure ())
where
step (s, k) () =
let k' = k + 1
finished = k' == n
s' = if finished then not s else s
k'' = if finished then 0 else k'
in ((s', k''), if s' then high else low)
Since it doesn't work when I upload it to a real FPGA board, I thought I'd try it in Xilinx's simulator, with the following testbench:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY testbench IS
END testbench;
ARCHITECTURE behavior OF testbench IS
COMPONENT blinkerTop
PORT(
CLK_32MHZ : IN std_logic;
RESET : IN std_logic;
LED : OUT std_logic
);
END COMPONENT;
signal CLK_32MHZ : std_logic := '0';
signal RESET : std_logic := '0';
signal LED : std_logic;
constant CLK_32MHZ_period : time := 31.2 ns;
BEGIN
uut: blinkerTop PORT MAP (
CLK_32MHZ => CLK_32MHZ,
RESET => RESET,
LED => LED
);
CLK_32MHZ_process :process
begin
CLK_32MHZ <= '0';
wait for CLK_32MHZ_period/2;
CLK_32MHZ <= '1';
wait for CLK_32MHZ_period/2;
end process;
END;
In the simulator, this matches the real life FPGA board's behaviour: the LED signal stays low.
I looked at the generated VHDL and this is what it looks like:
-- Automatically generated VHDL-93
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.ALL;
use std.textio.all;
use work.all;
use work.blinkertop_types.all;
entity blinkerTop is
port(-- clock
CLK_32MHZ : in std_logic;
-- asynchronous reset: active high
RESET : in std_logic;
LED : out std_logic);
end;
architecture structural of blinkerTop is
signal \#tup_app_arg\ : unsigned(31 downto 0);
signal \s'\ : boolean;
signal \#s'_case_alt\ : boolean;
signal s : boolean;
signal \#finished_case_alt\ : boolean;
signal \#k'_case_alt\ : unsigned(31 downto 0);
signal ds : blinkertop_types.tup2;
signal \#finished_app_arg\ : signed(63 downto 0);
signal x : unsigned(63 downto 0);
signal x_0 : blinkertop_types.tup2;
signal \x#\ : unsigned(63 downto 0);
signal k : unsigned(31 downto 0);
signal \#w\ : unsigned(63 downto 0);
begin
LED <= '1' when \s'\ else
'0';
\#tup_app_arg\ <= resize(to_unsigned(0,64),32) when \#finished_case_alt\ else
\#k'_case_alt\;
\s'\ <= \#s'_case_alt\ when \#finished_case_alt\ else
s;
\#s'_case_alt\ <= false when s else
true;
s <= ds.tup2_sel0;
\#finished_case_alt\ <= tagToEnum(\#finished_app_arg\);
\#w\ <= (\x#\ + to_unsigned(1,64));
\#k'_case_alt\ <= resize((resize(\#w\(31 downto 0),64)),32);
-- register begin
blinkertop_register : process(CLK_32MHZ,RESET)
begin
if RESET = '1' then
ds <= ( tup2_sel0 => false, tup2_sel1 => resize(to_unsigned(0,64),32) )
-- pragma translate_off
after 1 ps
-- pragma translate_on
;
elsif rising_edge(CLK_32MHZ) then
ds <= x_0
-- pragma translate_off
after 1 ps
-- pragma translate_on
;
end if;
end process;
-- register end
\#finished_app_arg\ <= to_signed(1,64) when x = to_unsigned(32000000,64) else to_signed(0,64);
x <= resize(\#k'_case_alt\,64);
x_0 <= ( tup2_sel0 => \s'\
, tup2_sel1 => \#tup_app_arg\ );
\x#\ <= resize(k,64);
k <= ds.tup2_sel1;
end;
I noticed that the internal state is not initialized, only assigned on reset. So this gave me an idea to add a reset process to the testbench:
stim_proc: process
begin
RESET <= '1';
wait for 100 ns;
RESET <= '0';
wait;
end process;
With this change, afterwards I see LED starting to blink in the simulator. [*]
That takes care of the simulation; but how would I ensure a similar reset signal on the real board?
[*] For the simulation, of course, I have increased the frequency from 32,000,000 cycles to just 100 cycles; otherwise I'd have to run the simulator for ages just to see the first transition.
One solution is to create a power-on-reset sequence in your FPGA logic. This can be implemented as a counter, and asserting reset as long as the counter value is below some constant. When the counter exceeds the constant value, deassert the reset.
I am writing a stop watch program on the Nexys4 FPGA. I can start, stop, and reset the stopwatch, but I'm having trouble implementing an increment feature. The increment feature is a button, that when pressed, will increment the clock by 1 millisecond. So if the seven segment display is showing 1:002 and the increment button is pressed, the display will show 1:003. Here is a snippet of my code for the counter:
always # (posedge (clk), posedge(rst))
begin
if (rst == 1'b1)begin
Dig0 <= 4'b0000;
Dig1 <= 4'b0000;
Dig2 <= 4'b0000;
Dig3 <= 4'b0000;
end
//increment if inc
else if(state == 2'b11)// && Dig3 < 4'b1001)begin
begin
Dig0 <= Dig0 + 4'b0001;
state <= 2'b00;
end
//only continue if Cen is 01 & not inc
else if(Cen == 2'b01)begin
//add 1 to first digit up till 9
Dig0 <= Dig0 + 1'b1;
//reset if == 10
if(Dig0 > 4'b1001)begin
Dig0 <= 4'b0000;
//add 1 to second digit (when first resets) up till 9
Dig1 <= Dig1 + 1'b1;
end
//reset if == 10
if(Dig1 == 4'b1010)begin
Dig1 <= 4'b0000;
//add 1 to third digit (when second reset) up till 9
Dig2 <= Dig2 + 1'b1;
end
//reset if == 10
if(Dig2 == 4'b1010)begin
Dig2 <= 4'b0000;
//add 1 to fourth digit (when third reset) up till 9
Dig3 <= Dig3 + 1'b1;
end
//reset if == 10
if(Dig3 > 4'b1001)begin
Dig3 <= 4'b0000;
end
end
Cen is coming from a state machine where state 2'b11 is increment, 2'b01 is count, and 2'b00 is stop. I can't figure out how to get it to increment just one bit. Whenever I hit increment is just counts forever. Any ideas?
Thanks
Without the state-machine code only I can only make a guess about the problem . You need to post the state-machine code too to conform the guess.
But the most probable reason for the counter continuing to increment is that Cen is also high (2'b01) while state is 2'b11.
Cycle 1 ) - state == 2'b11 , Cen == 2'b01
Dig0 +1 , state = 0
Cycle 2 ) - state = 0 , Cen == 2'b01
goes to else clause and the counter continues to increment
as long as Cen is 2'b01
There are also few issue you may need to fix .
1) in the increment section (state = 2'b11 ) you still need to check and increment all the 4 digits ( Dig0-3 ) as incrementing Dig0 ( more that 9 times ) will result in roll over to the next digit and so on.
2) Its better to update the state machine variables in a single always block. so its better to move the statement state = 2'b0 into the state-machine.
3) Also as already suggested in the comments you could have a single counter and decode it for digits.
I want to write a module for GCD computing, using extended Euclidean algorithm. But the main problem is that I completely don't know how to do that without getting to the lowest (RTL) level. What I mean is to have FSM with three states:
IDLE (waiting for input)
COMPUTING (as many clock cycles as needed)
FINISHED (ready to read output).
However, when I try to separate FSM & computations into separate processes, like this:
module modinv(clk, reset, number, prime, finished, gcd, inverse_fail, inverse);
input [31:0] number, prime;
input wire clk, reset;
output integer gcd, inverse;
output reg finished, inverse_fail;
parameter [2:0] IDLE = 3'b001, COMPUTING = 3'b010, END = 3'b100;
reg [2:0] state, state_next;
integer a, b, c, q, p, r;
always # (posedge clk, posedge reset)
begin
if (reset == 1)
begin
state <= IDLE;
end
else
begin
state <= state_next;
end
end
always #(state or b)
begin
finished <= 0;
inverse_fail <= 0;
case (state)
IDLE:
begin
a <= number;
b <= prime;
p <= 1;
r <= 0;
state_next <= COMPUTING;
end
COMPUTING:
begin
c = a % b;
q = a / b;
a = b;
b = c;
r = p - q * r;
p = r;
if (b == 0)
begin
state_next <= END;
end
else
begin
state_next <= COMPUTING;
end
end
END:
begin
gcd <= a;
inverse <= p;
finished <= 1;
if (gcd != 1)
begin
inverse_fail <= 1;
end
end
endcase
end
endmodule
And when I try to put computation in the second process, in COMPUTING state case, it only works once - what is correct in means of verilog, because until computing is done, state doesn't change, so the process isn't called again.
However, when I put computation in the first process, there isn't any non-ugly way to limit the computations only to correct STATE, which results in wrong output (as soon as FSM is in FINISHED state, the output is already incorrect - one step further).
So, my question is - how to do it correctly without using FSM + datapath (low-level RTL) solution?
My current waveform:
You seem to be missing some clocked elements in your design.
From what I understand of your design, you seem to expect once the state goes to COMPUTING, it should keep iterating the values of a and b until b reaches 0. But the only thing you're actually clocking on a clock edge is the state variable, so there's no memory of a and b from one state to the next. If you want variables like a and b to have memory from one clock cycle to the next, then you need to latch these variables as well:
I made some modifications to your program, it might not be 100% correct, but you should see what I'm getting at. See if this makes sense how you do the combinational logic in the second block, but you register the values on the posedge so that you can use them at the start of the next clock cycle.
module modinv(clk, reset, number, prime, finished, gcd, inverse_fail, inverse);
input [31:0] number, prime;
input wire clk, reset;
output integer gcd, inverse;
output reg finished, inverse_fail;
parameter [2:0] IDLE = 3'b001, COMPUTING = 3'b010, END = 3'b100;
reg [2:0] state, state_next;
integer a, b, c, q, p, r;
integer a_next, b_next, p_next, r_next;
always # (posedge clk, posedge reset)
begin
if (reset == 1)
begin
state <= IDLE;
a <= 0;
b <= 0;
p <= 0;
r <= 0;
end
else
begin
state <= state_next;
a <= a_next;
b <= b_next;
p <= p_next;
r <= r_next;
end
end
always #* //just use the auto-triggered '#*' operator
begin
finished <= 0;
inverse_fail <= 0;
case (state)
IDLE:
begin
a_next <= number;
b_next <= prime;
p_next <= 1;
r_next <= 0;
state_next <= COMPUTING;
end
COMPUTING:
begin
c = a % b;
q = a / b;
a_next = b;
b_next = c;
r_next = p - q * r;
p_next = r;
if (b == 0)
begin
state_next <= END;
end
else
begin
state_next <= COMPUTING;
end
end
END:
begin
gcd <= a;
inverse <= p;
finished <= 1;
if (gcd != 1)
begin
inverse_fail <= 1;
end
end
endcase
end
endmodule
I am modifying a simple keyboard interface I found on the net to my use. The idea is whenever there is a new scancode, it will make the output named "Scan_Dav" go high, and then go low. So when I direct Scan_Dav to another module as a clock, that module's clock will have a rising edge whenever a new ScanCode is pressed. Is there any error in my way of thinking? Because I tried it and directed the scancode and scan_dav to the rest of my project -which writes letters side by side with the given scancodes and shows them on seven segment display- the displayed text had 2 of each character ( i.e. when I write FLY the text was like FFLLYY). If there is no errors, I will share my code and ask you why it is not working. Thanks :)
EDIT: This is where the shifting is done according to values of Scan_Dav
signal bytes : std_logic_vector(63 downto 0);
signal Scan_Dav_Sync: std_logic_vector(1 downto 0):="00";
signal Previous_Scan_Dav: std_logic:='0';
begin
process (clk) begin --, Scan_Dav) begin
if rising_edge(clk) then
Scan_Dav_Sync(0) <= Scan_Dav;
Scan_Dav_Sync(1) <= Scan_Dav_Sync(0);
Previous_Scan_Dav <= Scan_Dav_Sync(1);
if (Previous_Scan_Dav = '0') and (Scan_Dav_Sync(1) = '1') then
bytes <= bytes (bytes'high-8 downto 0) & Data_in;
end if;
end if;
end process;
This is where Scan_Dav comes from, the code is taken from here:
(You may ignore the filtering part)
Architecture Behavioral of KeyboardController is
signal PS2_Datr : std_logic;
subtype Filter_t is std_logic_vector(7 downto 0);
signal Filter : Filter_t;
signal Fall_Clk : std_logic;
signal Bit_Cnt : unsigned (3 downto 0);
signal Scan_DAVi : std_logic;
signal S_Reg : std_logic_vector(8 downto 0);
signal PS2_Clk_f : std_logic;
Type State_t is (Idle, Shifting);
signal State : State_t;
signal Scan_Code : std_logic_vector(7 downto 0);
signal Flag : std_logic:='0';
begin
process (Clk,Reset)
begin
if Reset='1' then
PS2_Datr <= '0';
PS2_Clk_f <= '0';
Filter <= (others=>'0');
Fall_Clk <= '0';
elsif rising_edge (Clk) then
PS2_Datr <= PS2_Data and PS2_Data; -- also turns 'H' into '1'
Fall_Clk <= '0';
Filter <= (PS2_Clk and PS2_CLK) & Filter(Filter'high downto 1);
if Filter = Filter_t'(others=>'1') then
PS2_Clk_f <= '1';
elsif Filter = Filter_t'(others=>'0') then
PS2_Clk_f <= '0';
if PS2_Clk_f = '1' then
Fall_Clk <= '1';
end if;
end if;
end if;
end process;
-- This simple State Machine reads in the Serial Data
-- coming from the PS/2 peripheral.
process(Clk,Reset)
begin
if Reset='1' then
State <= Idle;
Bit_Cnt <= (others => '0');
S_Reg <= (others => '0');
Scan_Code <= (others => '0');
Scan_Out <= (others => '0');
Scan_Davi <= '0';
elsif rising_edge (Clk) then
-- if Scan_Davi = '1' then
-- Scan_Davi <= '0';
-- end if;
case State is
when Idle =>
Bit_Cnt <= (others => '0');
-- note that we dont need to clear the Shift Register
if Fall_Clk='1' and PS2_Datr='0' then -- Start bit
State <= Shifting;
end if;
when Shifting =>
if Bit_Cnt >= 9 then
if Fall_Clk='1' then -- Stop Bit
Scan_Code <= S_Reg(7 downto 0);
if (Flag = '1' and Scan_Code /= "11110000") then
--to ignore makecode
Scan_Out <= Scan_Code;
Flag <= '0';
Scan_Davi <= '1';
end if;
if (Flag = '0' and Scan_Code = "11110000") then
--to ignore F0
Flag <= '1';
Scan_Davi <= '0';
end if;
State <= Idle;
end if;
elsif Fall_Clk='1' then
Bit_Cnt <= Bit_Cnt + 1;
S_Reg <= PS2_Datr & S_Reg (S_Reg'high downto 1); -- Shift right
end if;
when others => -- never reached
State <= Idle;
end case;
end if;
end process;
Scan_DAV <= Scan_DAVi;
end Behavioral;
UPDATE: The only problem that remains is the delayed display and shifting of the letter and the text. While writing VHDL, I get nothing after pressing V, then I get V when I press H and it goes like that. The last letter does not appear until another key is pressed.It seems to be an issue about Scan_Dav, yet I can not resolve what it is. Any help will be appreciated.
Driving a clock input from logic output is generally bad practice (and some FPGA fabrics will not allow it at all). Clocks run best when sourced from dedicated clock logic inside the part, and good designs should minimize the number of clocks. Ideally you'd have only one, but that's not always possible.
Instead of running a clock input from logic, consider running everything off of one clock and use "enables" to activate the logic only when needed. In this case, you would detect the rising-edge transition of scan_dav inside of the downstream module and only react when that transition occurs. The detection logic would run off of the same clock as the scan_dav module.
I don't think this explains why you're seeing double characters, you would need to post some code to analyze. However, I would recommend that you re-tool to not drive clocks from logic.
If I see it right you avoid the F0 when you release the Key but you do not filter the second scancode.
It's always like this
Scancode --- press Key
F0 --- relesase Key
Scancode
on some Keys (e.g ALT GR) you can get an E0 too.
It not complete description but the most importand thinks are shown.
http://en.wikipedia.org/wiki/Scancode
This would lead to the descripted problem. FLY -> FFLLYY.