Verilog code adding two integers generated by a for loop - verilog

Question

How about this? I'm looking for an output i+j=1+2, 2+3... 4+5.
module add(i,j,b);
input [31:0] i, j; //32 bit unsigned
output [31:0] y;
task ADD(i, j, y);
begin
for (i= 1; i <= 4; i++)
begin
for(j=2; j <= 5; j++)
assign y = i + j;
end
end
$display("y ", y);
endtask
endmodule

Answer 1

Is this intended for synthesis? If so you should probably avoid using tasks until you have learnt when they can be used. I never use them in synthesisable code.
functions on the other hand are often used for synthesis but can not contain timing information. Ie a function can only represent combinatorial logic, that all happens in an instant.
1) That is not how you use assign. The correct use would be:
wire [9:0] a;
assign a = 10'b0;
//or
//a,b both 10 bits driven from other logic
wire [9:0] sum;
assign sum = a + b;
Note how you assign to a wire, this is combinatorial.
2) Your display is outside of the for loop it will only display once at the end.
I would have done this some thing like:
module add(
input [31:0] a,
input [31:0] b,
output [31:0] sum
);
assign sum = a + b ;
endmodule
module testharness();
reg [31:0] a;
reg [31:0] b;
wire [31:0] sum;
reg clock;
// Make clock toggle every 10ns (20ns clock period)
initial begin
clock = 0;
forever begin
#10ns clock= ~clock;
end
end
//DUT (Device Under Test)
add add_0 (
.a ( a ),
.b ( b ),
.sum ( sum )
);
// Test program
initial begin
a=0;
b=0;
#(posedge clock);
$display( "a (%2d) + b (%2d) = sum (%2d)", a, b, sum );
a=1;
b=2;
#(posedge clock);
$display( "a (%2d) + b (%2d) = sum (%2d)", a, b, sum );
a=3;
b=4;
#(posedge clock);
$display( "a (%2d) + b (%2d) = sum (%2d)", a, b, sum );
$finish;
end
endmodule
Note how we have used time to separate the results, for more complicated designs you may use flip-flops which means you only get a new result per clock. Or per rising and falling edge if using DDR techniques.
You can now try to modify the test program section to stimulate the DUT as per your requirements.