Verilog 3 bit concentrate of 2 variables - verilog

Question

I am Trying to understand this bit of Verilog code..
reg [2:0] SYNC;
always #(posedge clk) SYNC <= {SYNC[1:0], ASYNC};
wire SYNC_risingedge = (SYNC[2:1] == 2'b01);
wire SYNC_fallingedge = (SYNC[2:1] == 2'b10);
wire SYNC_on = ~SYNC[1];
From what i understand.
A 3 bit reg is made (sync)
When the clock rises, sync is equal to the combination of bits 1 and 0 with the current value of (async).
The SYNC_risingedge is equal to (sync) bits 2 and 1 and the value of binary '01'
The SYNC_fallingedge is equal to (sync) bits 2 and 1 and the value of binary '10'
The SYNC_on is equal to the inverse of sync.
My questions are next to the lines in quotes.
reg [2:0] SYNC;
always #(posedge clk) SYNC <= {SYNC[1:0], ASYNC}; *"does this mean that it concentrates the state of ASYNC with only bits 1 and 0?"*
wire SYNC_risingedge = (SYNC[2:1] == 2'b01); *"is the binary number 01 placed only in bits 2 and 1? if so, how does it affect the previous line?"*
wire SYNC_fallingedge = (SYNC[2:1] == 2'b10); *"same question as previous line"*
wire SYNC_on = ~SYNC[1]; *"What does the [1] mean in ~SYNC[1]?"*
I've scoured the web, looking for Verilog syntax to understand this bit of code, but have come up short.
Any assistance would be appreciated.

Answer 1

Question 1
always #(posedge clk) SYNC <= {SYNC[1:0], ASYNC};
does this mean that it concentrates the state of ASYNC with only bits 1 and 0?
I think you mean "concatenates", and you're about right, yes. This statement essentially left-shifts SYNC by 1 and then puts the value of ASYNC in bit 0. This shifting operation takes place on each rising clock edge.
Complete table:
SYNC | ASYNC | New SYNC Setting
---------+-----------|--------------------
000 | 0 | 000
001 | 0 | 010
010 | 0 | 100
011 | 0 | 110
100 | 0 | 000
101 | 0 | 010
110 | 0 | 100
111 | 0 | 110
000 | 1 | 001
001 | 1 | 011
010 | 1 | 101
011 | 1 | 111
100 | 1 | 001
101 | 1 | 011
110 | 1 | 101
111 | 1 | 111
Question 2
wire SYNC_risingedge = (SYNC[2:1] == 2'b01);
is the binary number 01 placed only in bits 2 and 1? if so, how does it affect the previous line?
No, the == is a test, not an assignment. If those two bits of SYNC match 2b'01, then the SYNC_risingedge wire will be high. Otherwise it will be low.
Note: the "assignment" to SYNC_risingedge is asynchronous - it's just combinational logic.
Question 3
wire SYNC_fallingedge = (SYNC[2:1] == 2'b10);
same question as previous line
Same answer, too.
Question 4
wire SYNC_on = ~SYNC[1];
What does the [1] mean in ~SYNC[1]?
It's just referring to bit 1 of SYNC. SYNC_on is high whenever SYNC[1] is low, and vice versa.