This is my first time on stackoverflow.com and new to verilog coding. I may use some terms incorrectly so if I do please correct me so I can be clearer in future posts.
I am using an Altera FPGA board where there are 7 LEDG lights which can be triggered on and off. For my project I am making a BCD adder where LEDG [7] turns on when the BCD value is not 0 - 9. However, I don't want to declare outputs [6:4]. LEDG[3:0] displays the binary equivalent of the summation of the two inputs.
I thought I could use two separate declaration statements but it tells me that LEDG is already declared which it is. I then tried to combine it using brackets but it also complained about that. Is there any way to simplify my code. Below are examples of what I've tried.
Example 1:
module BCD (..., LEDG, ...);
output reg [3:0] LEDG;
output reg [7] LEDG;
endmodule
Example 2:
module BCD (..., LEDG, ...);
output reg ({[3:0], [7]} LEDG);
endmodule
Any help would be greatly appreciated! Thanks in advance. :-)
What you're trying to do is not possible, if you're going to output a bus then you must specify a single contiguous range.
You should just declare an output reg [7:0] if you need to output [7] and [3:0].
You can leave the unused bits undriven, or if that gives a synthesis warning/error then tie them off to 0 or 1 if you don't care about their value (LEDG[6:4] = 3'b0).
module(...NBCD_FLAG, LEDG...);
output reg [3:0] LEDG;
output wire NBCD_FLAG;
In your .qsf file assign LEDG to leds 3-0 on you board
and NBED_FLAG to led 7.
This way you can use led 6-4 for some other purpose.
Related
I am trying to invert a 64-bit variable in verilog, but for some reason only one bit is inverted.
wire [63:0] bc;
assign bc = 64'b0;
assign notbc = ~bc;
I'm expecting the output to 64 bits of one's, but instead I get the most significant bit to be 1 and the others are 0's.
I also tried something else I found online:
assign notbc = bc ^ 64'b1;
but what I get this time is that the least significant bit is one and the others are 0's. What can I do to get the negation of every bit i.e. 64 bits of 1's?
Note: I'm limited to Verilog, I can't use SystemVerilog.
Here is the full module:
`timescale 1ns/1ns
module notting(
output [63:0] out);
wire [63:0] bc;
assign bc = 64'b0;
assign out = ~bc;
endmodule
It might just be missing from the code you pasted, but since notbc is not declared, it will be implicitly declared as a single-bit wire. With the following code you should be getting 64 ones, unless there is a problem with your simulator:
wire [63:0] bc, notbc;
assign bc = 64'b0;
assign notbc = ~bc;
I have checked your code in cloudv.io.
I have checked it works for small bitwidth
However, as I increased the bitwidth, the bug came out.
At this point I am not sure what causes the bug as I am not friendly with the system.
It seems like the bug can be reproduced when input is over fifty some bit wide.
Are these two lines of code in verilog the same?
output[1:0] r;
reg[1:0] r;
output[1:0] r;
reg r;
Do the number of bits have to be declared twice?
No. No No.
Verilog offers a few styles of declaring ports. The recommend way is known as ANSI-style, where you only mention the port name once.
module m(output reg [1:0] r, input clk);
It unfortunate that this style does not appear first in the LRM.
And, yes using the style in your question requires that the bit widths match.
I'm a just starting to learn verilog , and I'm having trouble with some things. I've found a few resources to help, but there are some things which aren't clear and I need specified. I have code for a D Flip-flop below. And I understand how the declaration for in and out work. What I dont get is the register.
When it says out is the variable associated with it.Does this association mean, out is the register along with output? Or does it mean out is also the output for the register?
module DFF(quarter, in, out) ;
parameter n = 1; // width
input quarter ;
input [n-1:0] in ;
output [n-1:0] out ;
reg [n-1:0] out ;
always #(quarter=1)
out = in ;
endmodule
In Verilog there are nets and there are variables. The most common kind of net by far is a wire, which you're probably familiar with. You can declare a variable using var, but most people say reg, because that is how it always has been done.
(In Verilog, but not in SystemVerilog), wires have to be driven by
assign statements
the outputs of instantiated modules
and variables have to be driven from
initial and always blocks.
Your output out is driven from an always block and so must be a variable. The line
reg [n-1:0] out ;
declares the output out as being a variable (rather than a wire).
In fact, you are using an old-fashioned way of specifying inputs and outputs. Since 2001, the way to do it is like this:
module DFF #(parameter n = 1)
(input wire quarter,
input wire [n-1:0] in,
output reg [n-1:0] out);
always #(quarter=1)
out = in ;
endmodule
This is the so-called ANSI form and, I think you would agree, is more sensible. I would advise using this form, not the old-fashioned form you are using.
BTW, you code is a bit strange. I'm not entirely sure what it's supposed to do, but this if you're expecting output to be driven by in when quarter is 1, I'd do it more like this:
module DFF // #(parameter n = 1) // you're not using parameter n
(input wire quarter,
input wire [n-1:0] in,
output reg [n-1:0] out);
always #(*)
if (quarter == 1'b1)
out = in ;
else
// IMPORTANT ! : what is out when quarter != 1 ?
// your current code would synthesise to a latch
// is that what you wanted? (And if so, are you
// sure that's what you wanted)
endmodule
initially verilog was though as a language which does behavioral types of operation on state variables (registers, reg) and connects them via nets. So, reg is a variable which is supposed to keep its value between operations, net is just a connection and has no state associated with it, i.e. wire. reg values can be calculated in procedural blocks, i.e. always block, wires can be connected only (using continuous assignments, assign statements (outside of the always blocks)).
There are different rules for using for regs and wires and different behavior of them in simulation, in particular around multiple drivers. See Matthew's reply for more info.
I have just started using Verilog and I was wondering if there is a way to do the following:
If I have three two bit wires where testmux connects to muxt in its index one bit and muxt connects to muxt2 in its index one bit, is there a way to access the "1" bit within muxt2 through an assignment based on only testmux? I naively tried using the very last line in the snippet of code below, but it does not seem to work, even with parentheses. Any guidance would be greatly appreciated, thank you in advance.
output test;
wire [1:0] testmux = {muxt,1'b0};
wire [1:0] muxt = {muxt2,1'b0};
wire [1:0] muxt2 = {1'b1,1'b0};
assign test = testmux[1][1][1];
Crude Diagram
The there is no way to do it the way you want. You really created a hierarchical wiring, but the array access is only allowed on a flat wire. There is no way in verilog to do such a hierarchical expressions.
If i understand your intent correctly, the only need to access the upper bit of the muxt2. BTW, you also need to change the order of declarations. The wires must be declared before they are used.
output test;
wire [1:0] muxt2 = {1'b1,1'b0};
wire [1:0] muxt = {muxt2,1'b0};
wire [1:0] testmux = {muxt,1'b0};
assign test = muxt2[1];
Coming from a C++ background I'm starting to learn Verilog. This code describes four inputs going into two AND gates. The outputs from those two AND gates go into an OR gate. The output from the OR gate is the final output.
// a user-defined AND gate
module my_and2 (in, out);
input [1:0] in;
output out;
assign out = in[1]&in[0];
endmodule
// a user-defined OR gate
module my_or2 (in, out);
input [1:0] in;
output out;
assign out = in[1]|in[0];
endmodule
// the AND-OR logic built on top of the user-defined AND and OR gates
module and_or (in_top, out_top);
input [3:0] in_top;
output out_top;
wire [1:0] sig;
// instantiate the gate-level modules
my_and2 U1 (.in(in_top[3:2]),.out(sig[1]));
my_and2 U2 (.in(in_top[1:0]),.out(sig[0]));
my_or2 U3 (.in(sig),.out(out_top));
endmodule
The first two modules make sense to me. However, the last one doesn't. The first two modules have an assign statement at the end to set the value for the output variable. However, the last one doesn't. Why is that?
Verilog is 'event driven'. When writing verilog, think in terms of sensitivity lists.
In your example of the AND gate, you've the expression assign out = in[1]&in[0];. Your expression is said to be sensitive to in[0] and in[1]. This means that any time in[0] or in[1] change, the expression will be recomputed, and the value of out will be updated.
So in your toplevel module and_or, you're basically building a big tree of expressions that are sensitive to the outputs of the preceding expressions. This tree is, of course, built using the module connections. So a change in the value of one of the inputs to this toplevel module will ripple through all expressions in its 'logic cone'.
To drive the inputs you'll need higher level testbench module driving signals into your and_or module. This will supply inputs spaced out in time which will trigger the expressions in and below and_or. If not, your sim will have no events, so no expressions will trigger and the sim will time-out at 0ps because it is 'event starved'.
PS: for your AND gate expression, assign out = ∈ will work too... (reduction AND operator)
out_top is driven by the U3 instance output.
To put things simply, I like to think instantiation as just connecting wires.
Modules are blocks of digital circuits. You AND and OR gate modules are where magic happens. You already understand that part. By instantiating those modules, it's like you're connecting the input wires of your top level module with inputs of two blocks AND module. Then taking the outputs of them and taping them to the input wire sticking out of your OR block. And finally you're connecting the output of OR block to the output signal wire of top level.